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We currently call mdp5_pipe_assign() twice to assign the left and right hwpipes for our drm_plane. When merging 2 hwpipes, there are a few constraints that we need to keep in mind: - Only the same types of SSPPs are preferred. I.e, a RGB pipe should be paired with another RGB pipe, VIG with VIG etc. - The hwpipe staged on the left should have a higher priority than the hwpipe staged on the right. The priorities are as follows: VIG0 > VIG1 > VIG2 > VIG3 RGB0 > RGB1 > RGB2 > RGB3 DMA0 > DMA1 We can't apply these constraints easily if mdp5_pipe_assign() is called twice. Update mdp5_pipe_assign() to find both hwpipes in one go, and add the extra constraints needed. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
58 lines
1.7 KiB
C
58 lines
1.7 KiB
C
/*
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* Copyright (C) 2016 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MDP5_PIPE_H__
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#define __MDP5_PIPE_H__
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/* TODO: Add SSPP_MAX in mdp5.xml.h */
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#define SSPP_MAX (SSPP_CURSOR1 + 1)
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/* represents a hw pipe, which is dynamically assigned to a plane */
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struct mdp5_hw_pipe {
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int idx;
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const char *name;
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enum mdp5_pipe pipe;
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uint32_t reg_offset;
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uint32_t caps;
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uint32_t flush_mask; /* used to commit pipe registers */
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/* number of smp blocks per plane, ie:
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* nblks_y | (nblks_u << 8) | (nblks_v << 16)
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*/
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uint32_t blkcfg;
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};
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/* global atomic state of assignment between pipes and planes: */
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struct mdp5_hw_pipe_state {
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struct drm_plane *hwpipe_to_plane[SSPP_MAX];
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};
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int mdp5_pipe_assign(struct drm_atomic_state *s, struct drm_plane *plane,
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uint32_t caps, uint32_t blkcfg,
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struct mdp5_hw_pipe **hwpipe,
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struct mdp5_hw_pipe **r_hwpipe);
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void mdp5_pipe_release(struct drm_atomic_state *s, struct mdp5_hw_pipe *hwpipe);
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struct mdp5_hw_pipe *mdp5_pipe_init(enum mdp5_pipe pipe,
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uint32_t reg_offset, uint32_t caps);
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void mdp5_pipe_destroy(struct mdp5_hw_pipe *hwpipe);
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#endif /* __MDP5_PIPE_H__ */
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