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The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it so that those IRQs can then be linked to the related GPIOs. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/7708243d6cca21004de8b3da87369c06dbee3848.1767804922.git.chleroy@kernel.org Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> [moved from bindings/soc/fsl/cpm_qe/ to bindings/interrupt-controller/ while applying]
52 lines
981 B
YAML
52 lines
981 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/fsl,qe-ports-ic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale QUICC Engine I/O Ports Interrupt Controller
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maintainers:
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- Christophe Leroy (CS GROUP) <chleroy@kernel.org>
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properties:
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compatible:
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enum:
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- fsl,mpc8323-qe-ports-ic
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reg:
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maxItems: 1
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interrupt-controller: true
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'#address-cells':
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const: 0
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'#interrupt-cells':
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const: 1
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#address-cells'
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- '#interrupt-cells'
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- interrupts
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additionalProperties: false
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examples:
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- |
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interrupt-controller@c00 {
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compatible = "fsl,mpc8323-qe-ports-ic";
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reg = <0xc00 0x18>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupts = <74 0x8>;
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interrupt-parent = <&ipic>;
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};
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