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f0ceedd52a
Firmware contants do not fit the purpose of bindings because they are not
independent IDs for abstractions. They are more or less just contants which
better to wire via header with DT which is using it.
That's why add deprecated message to dt binding header and also update
existing dt bindings not to use macros from the header and replace them by
it's value. Actually value is not relevant because it is only example.
The similar changes have been done by commit 9d92925768 ("dt-bindings:
pinctrl: samsung: deprecate header with register constants").
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2a6f0229522327939e6893565e540b75f854a37b.1738600745.git.michal.simek@amd.com
136 lines
3.2 KiB
YAML
136 lines
3.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx SuperSpeed DWC3 USB SoC controller
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maintainers:
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- Mubin Sayyed <mubin.sayyed@amd.com>
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- Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
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properties:
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compatible:
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items:
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- enum:
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- xlnx,zynqmp-dwc3
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- xlnx,versal-dwc3
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reg:
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maxItems: 1
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"#address-cells":
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enum: [ 1, 2 ]
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"#size-cells":
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enum: [ 1, 2 ]
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ranges: true
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power-domains:
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description: specifies a phandle to PM domain provider node
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maxItems: 1
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clocks:
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description:
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A list of phandle and clock-specifier pairs for the clocks
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listed in clock-names.
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items:
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- description: Master/Core clock, has to be >= 125 MHz
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for SS operation and >= 60MHz for HS operation.
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- description: Clock source to core during PHY power down.
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clock-names:
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items:
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- const: bus_clk
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- const: ref_clk
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resets:
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description:
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A list of phandles for resets listed in reset-names.
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items:
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- description: USB core reset
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- description: USB hibernation reset
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- description: USB APB reset
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reset-names:
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items:
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- const: usb_crst
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- const: usb_hibrst
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- const: usb_apbrst
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phys:
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minItems: 1
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maxItems: 2
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phy-names:
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minItems: 1
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maxItems: 2
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items:
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enum:
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- usb2-phy
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- usb3-phy
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reset-gpios:
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description: GPIO used for the reset ulpi-phy
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maxItems: 1
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# Required child node:
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patternProperties:
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"^usb@[0-9a-f]+$":
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$ref: snps,dwc3.yaml#
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- ranges
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- power-domains
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- clocks
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- clock-names
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- resets
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- reset-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
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#include <dt-bindings/power/xlnx-zynqmp-power.h>
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#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
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#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
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#include <dt-bindings/phy/phy.h>
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axi {
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#address-cells = <2>;
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#size-cells = <2>;
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usb@0 {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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compatible = "xlnx,zynqmp-dwc3";
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reg = <0x0 0xff9d0000 0x0 0x100>;
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clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>;
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clock-names = "bus_clk", "ref_clk";
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power-domains = <&zynqmp_firmware PD_USB_0>;
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resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
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<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
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<&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
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reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
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phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
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phy-names = "usb3-phy";
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ranges;
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usb@fe200000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfe200000 0x0 0x40000>;
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interrupt-names = "host", "otg";
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interrupts = <0 65 4>, <0 69 4>;
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dr_mode = "host";
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dma-coherent;
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};
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};
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};
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