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SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a
top level wrapper consisting of Display Processing Unit (DPU) and
display peripheral modules such as Display Serial Interface (DSI)
and DisplayPort (DP).
MDSS functions essentially as a back-end composition engine. It blends
video and graphic images stored in the frame buffers and scans out the
composed image to a display sink (over DSI/DP).
The following diagram represents hardware blocks for a simple pipeline
(two planes are present on a given crtc which is connected to a DSI
connector):
MDSS
+---------------------------------+
| +-----------------------------+ |
| | DPU | |
| | +--------+ +--------+ | |
| | | SSPP | | SSPP | | |
| | +----+---+ +----+---+ | |
| | | | | |
| | +----v-----------v---+ | |
| | | Layer Mixer (LM) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | PingPong (PP) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | INTERFACE (VIDEO) | | |
| | +---+----------------+ | |
| +------|----------------------+ |
| | |
| +------|---------------------+ |
| | | DISPLAY PERIPHERALS | |
| | +---v-+ +-----+ | |
| | | DSI | | DP | | |
| | +-----+ +-----+ | |
| +----------------------------+ |
+---------------------------------+
The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs)
depends on SoC capabilities.
Overview of DPU sub-blocks:
---------------------------
* Source Surface Processor (SSPP):
Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are
capable of performing format conversion, scaling and quality improvement
for source surfaces.
* Layer Mixer (LM):
Blend source surfaces together (in requested zorder)
* PingPong (PP):
This block controls frame done interrupt output, EOL and EOF generation,
overflow/underflow control.
* Display interface (INTF):
Timing generator and interface connecting the display peripherals.
DRM components mapping to DPU architecture:
------------------------------------------
PLANEs maps to SSPPs
CRTC maps to LMs
Encoder maps to PPs, INTFs
Data flow setup:
---------------
MDSS hardware can support various data flows (e.g.):
- Dual pipe: Output from two LMs combined to single display.
- Split display: Output from two LMs connected to two separate
interfaces.
The hardware capabilities determine the number of concurrent data paths
possible. Any control path (i.e. pipeline w/i DPU) can be routed to any
of the hardware data paths. A given control path can be triggered,
flushed and controlled independently.
Changes in v3:
- Move msm_media_info.h from uapi to dpu/ subdir
- Remove preclose callback dpu (it's handled in core)
- Fix kbuild warnings with parent_ops
- Remove unused functions from dpu_core_irq
- Rename mdss_phys to mdss
- Rename mdp_phys address space to mdp
- Drop _phys from vbif and regdma binding names
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
[robclark minor rebase]
Signed-off-by: Rob Clark <robdclark@gmail.com>
140 lines
3.7 KiB
C
140 lines
3.7 KiB
C
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DPU_HW_CDM_H
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#define _DPU_HW_CDM_H
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#include "dpu_hw_mdss.h"
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#include "dpu_hw_top.h"
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#include "dpu_hw_blk.h"
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struct dpu_hw_cdm;
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struct dpu_hw_cdm_cfg {
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u32 output_width;
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u32 output_height;
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u32 output_bit_depth;
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u32 h_cdwn_type;
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u32 v_cdwn_type;
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const struct dpu_format *output_fmt;
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u32 output_type;
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int flags;
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};
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enum dpu_hw_cdwn_type {
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CDM_CDWN_DISABLE,
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CDM_CDWN_PIXEL_DROP,
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CDM_CDWN_AVG,
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CDM_CDWN_COSITE,
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CDM_CDWN_OFFSITE,
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};
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enum dpu_hw_cdwn_output_type {
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CDM_CDWN_OUTPUT_HDMI,
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CDM_CDWN_OUTPUT_WB,
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};
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enum dpu_hw_cdwn_output_bit_depth {
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CDM_CDWN_OUTPUT_8BIT,
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CDM_CDWN_OUTPUT_10BIT,
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};
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/**
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* struct dpu_hw_cdm_ops : Interface to the chroma down Hw driver functions
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* Assumption is these functions will be called after
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* clocks are enabled
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* @setup_csc: Programs the csc matrix
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* @setup_cdwn: Sets up the chroma down sub module
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* @enable: Enables the output to interface and programs the
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* output packer
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* @disable: Puts the cdm in bypass mode
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*/
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struct dpu_hw_cdm_ops {
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/**
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* Programs the CSC matrix for conversion from RGB space to YUV space,
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* it is optional to call this function as this matrix is automatically
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* set during initialization, user should call this if it wants
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* to program a different matrix than default matrix.
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* @cdm: Pointer to the chroma down context structure
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* @data Pointer to CSC configuration data
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* return: 0 if success; error code otherwise
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*/
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int (*setup_csc_data)(struct dpu_hw_cdm *cdm,
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struct dpu_csc_cfg *data);
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/**
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* Programs the Chroma downsample part.
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* @cdm Pointer to chroma down context
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*/
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int (*setup_cdwn)(struct dpu_hw_cdm *cdm,
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struct dpu_hw_cdm_cfg *cfg);
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/**
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* Enable the CDM module
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* @cdm Pointer to chroma down context
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*/
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int (*enable)(struct dpu_hw_cdm *cdm,
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struct dpu_hw_cdm_cfg *cfg);
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/**
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* Disable the CDM module
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* @cdm Pointer to chroma down context
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*/
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void (*disable)(struct dpu_hw_cdm *cdm);
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};
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struct dpu_hw_cdm {
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struct dpu_hw_blk base;
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struct dpu_hw_blk_reg_map hw;
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/* chroma down */
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const struct dpu_cdm_cfg *caps;
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enum dpu_cdm idx;
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/* mdp top hw driver */
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struct dpu_hw_mdp *hw_mdp;
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/* ops */
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struct dpu_hw_cdm_ops ops;
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};
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/**
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* dpu_hw_cdm - convert base object dpu_hw_base to container
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* @hw: Pointer to base hardware block
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* return: Pointer to hardware block container
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*/
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static inline struct dpu_hw_cdm *to_dpu_hw_cdm(struct dpu_hw_blk *hw)
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{
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return container_of(hw, struct dpu_hw_cdm, base);
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}
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/**
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* dpu_hw_cdm_init - initializes the cdm hw driver object.
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* should be called once before accessing every cdm.
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* @idx: cdm index for which driver object is required
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* @addr: mapped register io address of MDP
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* @m : pointer to mdss catalog data
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* @hw_mdp: pointer to mdp top hw driver object
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*/
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struct dpu_hw_cdm *dpu_hw_cdm_init(enum dpu_cdm idx,
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void __iomem *addr,
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struct dpu_mdss_cfg *m,
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struct dpu_hw_mdp *hw_mdp);
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/**
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* dpu_hw_cdm_destroy - destroys CDM driver context
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* @cdm: pointer to CDM driver context
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*/
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void dpu_hw_cdm_destroy(struct dpu_hw_cdm *cdm);
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#endif /*_DPU_HW_CDM_H */
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