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98f44cb065
This patch adds support for new FullMAC WiFi driver for Quantenna QSR10G chipsets. QSR10G (aka Pearl) is Quantenna's 8x8, 160M, 11ac offering. QSR10G supports 2 simultaneous WMACs - one 5G and one 2G. 5G WMAC supports 160M, 8x8 configuration. FW supports up to 8 concurrent virtual interfaces on each WMAC. Patch introduces 2 new drivers: - qtnfmac.ko for interfacing with kernel wireless core - qtnfmac_pearl_pcie.ko for interfacing with hardware over PCIe interface Signed-off-by: Dmitrii Lebed <dlebed@quantenna.com> Signed-off-by: Sergei Maksimenko <smaksimenko@quantenna.com> Signed-off-by: Sergey Matyukevich <smatyukevich@quantenna.com> Signed-off-by: Bindu Therthala <btherthala@quantenna.com> Signed-off-by: Huizhao Wang <hwang@quantenna.com> Signed-off-by: Kamlesh Rath <krath@quantenna.com> Signed-off-by: Avinash Patil <avinashp@quantenna.com> Signed-off-by: Igor Mitsyanko <igor.mitsyanko.os@quantenna.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
90 lines
1.9 KiB
C
90 lines
1.9 KiB
C
/*
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* Copyright (c) 2015-2016 Quantenna Communications, Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _QTN_FMAC_PCIE_H_
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#define _QTN_FMAC_PCIE_H_
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include "pcie_regs_pearl.h"
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#include "pcie_ipc.h"
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#include "shm_ipc.h"
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struct bus;
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struct qtnf_pcie_bus_priv {
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struct pci_dev *pdev;
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/* lock for irq configuration changes */
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spinlock_t irq_lock;
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/* lock for tx operations */
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spinlock_t tx_lock;
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u8 msi_enabled;
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int mps;
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struct workqueue_struct *workqueue;
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struct tasklet_struct reclaim_tq;
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void __iomem *sysctl_bar;
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void __iomem *epmem_bar;
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void __iomem *dmareg_bar;
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struct qtnf_shm_ipc shm_ipc_ep_in;
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struct qtnf_shm_ipc shm_ipc_ep_out;
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struct qtnf_pcie_bda __iomem *bda;
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void __iomem *pcie_reg_base;
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u16 tx_bd_num;
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u16 rx_bd_num;
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struct sk_buff **tx_skb;
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struct sk_buff **rx_skb;
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struct qtnf_tx_bd *tx_bd_vbase;
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dma_addr_t tx_bd_pbase;
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struct qtnf_rx_bd *rx_bd_vbase;
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dma_addr_t rx_bd_pbase;
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dma_addr_t bd_table_paddr;
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void *bd_table_vaddr;
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u32 bd_table_len;
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u32 hw_txproc_wr_ptr;
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u16 tx_bd_reclaim_start;
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u16 tx_bd_index;
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u32 tx_queue_len;
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u16 rx_bd_index;
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u32 pcie_irq_mask;
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/* diagnostics stats */
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u32 pcie_irq_count;
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u32 pcie_irq_rx_count;
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u32 pcie_irq_tx_count;
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u32 tx_full_count;
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u32 tx_done_count;
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u32 tx_reclaim_done;
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u32 tx_reclaim_req;
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};
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#endif /* _QTN_FMAC_PCIE_H_ */
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