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01389846f7
We need to be able to do both MMIO and DSB based pipe/plane
programming. To that end plumb the 'dsb' all way from the top
into the plane commit hooks.
The compiler appears smart enough to combine the branches from
all the back-to-back register writes into a single branch.
So the generated asm ends up looking more or less like this:
plane_hook()
{
if (dsb) {
intel_dsb_reg_write();
intel_dsb_reg_write();
...
} else {
intel_de_write_fw();
intel_de_write_fw();
...
}
}
which seems like a reasonably efficient way to do this.
An alternative I was also considering is some kind of closure
(register write function + display vs. dsb pointer passed to it).
That does result is smaller code as there are no branches anymore,
but having each register access go via function pointer sounds
less efficient.
Not that I actually measured the overhead of either approach yet.
Also the reg_rw tracepoint seems to be making a huge mess of the
generated code for the mmio path. And additionally there's some
kind of IS_GSI_REG() hack in __raw_uncore_read() which ends up
generating a pointless branch for every mmio register access.
So looks like there might be quite a bit of room for improvement
in the mmio path still.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240930170415.23841-12-ville.syrjala@linux.intel.com
248 lines
6.6 KiB
C
248 lines
6.6 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DE_H__
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#define __INTEL_DE_H__
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "intel_dsb.h"
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#include "intel_uncore.h"
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static inline struct intel_uncore *__to_uncore(struct intel_display *display)
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{
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return &to_i915(display->drm)->uncore;
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}
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static inline u32
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__intel_de_read(struct intel_display *display, i915_reg_t reg)
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{
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u32 val;
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intel_dmc_wl_get(display, reg);
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val = intel_uncore_read(__to_uncore(display), reg);
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intel_dmc_wl_put(display, reg);
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return val;
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}
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#define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), __VA_ARGS__)
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static inline u8
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__intel_de_read8(struct intel_display *display, i915_reg_t reg)
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{
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u8 val;
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intel_dmc_wl_get(display, reg);
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val = intel_uncore_read8(__to_uncore(display), reg);
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intel_dmc_wl_put(display, reg);
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return val;
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}
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#define intel_de_read8(p,...) __intel_de_read8(__to_intel_display(p), __VA_ARGS__)
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static inline u64
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__intel_de_read64_2x32(struct intel_display *display,
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i915_reg_t lower_reg, i915_reg_t upper_reg)
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{
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u64 val;
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intel_dmc_wl_get(display, lower_reg);
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intel_dmc_wl_get(display, upper_reg);
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val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,
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upper_reg);
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intel_dmc_wl_put(display, upper_reg);
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intel_dmc_wl_put(display, lower_reg);
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return val;
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}
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#define intel_de_read64_2x32(p,...) __intel_de_read64_2x32(__to_intel_display(p), __VA_ARGS__)
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static inline void
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__intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
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{
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intel_dmc_wl_get(display, reg);
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intel_uncore_posting_read(__to_uncore(display), reg);
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intel_dmc_wl_put(display, reg);
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}
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#define intel_de_posting_read(p,...) __intel_de_posting_read(__to_intel_display(p), __VA_ARGS__)
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static inline void
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__intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
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{
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intel_dmc_wl_get(display, reg);
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intel_uncore_write(__to_uncore(display), reg, val);
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intel_dmc_wl_put(display, reg);
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}
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#define intel_de_write(p,...) __intel_de_write(__to_intel_display(p), __VA_ARGS__)
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static inline u32
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____intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
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u32 clear, u32 set)
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{
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return intel_uncore_rmw(__to_uncore(display), reg, clear, set);
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}
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#define __intel_de_rmw_nowl(p,...) ____intel_de_rmw_nowl(__to_intel_display(p), __VA_ARGS__)
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static inline u32
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__intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear,
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u32 set)
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{
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u32 val;
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intel_dmc_wl_get(display, reg);
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val = __intel_de_rmw_nowl(display, reg, clear, set);
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intel_dmc_wl_put(display, reg);
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return val;
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}
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#define intel_de_rmw(p,...) __intel_de_rmw(__to_intel_display(p), __VA_ARGS__)
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static inline int
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____intel_de_wait_for_register_nowl(struct intel_display *display,
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i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout)
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{
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return intel_wait_for_register(__to_uncore(display), reg, mask,
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value, timeout);
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}
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#define __intel_de_wait_for_register_nowl(p,...) ____intel_de_wait_for_register_nowl(__to_intel_display(p), __VA_ARGS__)
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static inline int
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__intel_de_wait(struct intel_display *display, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout)
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{
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int ret;
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intel_dmc_wl_get(display, reg);
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ret = __intel_de_wait_for_register_nowl(display, reg, mask, value,
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timeout);
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intel_dmc_wl_put(display, reg);
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return ret;
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}
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#define intel_de_wait(p,...) __intel_de_wait(__to_intel_display(p), __VA_ARGS__)
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static inline int
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__intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
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u32 mask, u32 value, unsigned int timeout)
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{
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int ret;
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intel_dmc_wl_get(display, reg);
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ret = intel_wait_for_register_fw(__to_uncore(display), reg, mask,
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value, timeout);
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intel_dmc_wl_put(display, reg);
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return ret;
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}
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#define intel_de_wait_fw(p,...) __intel_de_wait_fw(__to_intel_display(p), __VA_ARGS__)
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static inline int
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__intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
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u32 mask, u32 value,
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unsigned int fast_timeout_us,
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unsigned int slow_timeout_ms, u32 *out_value)
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{
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int ret;
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intel_dmc_wl_get(display, reg);
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ret = __intel_wait_for_register(__to_uncore(display), reg, mask,
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value,
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fast_timeout_us, slow_timeout_ms, out_value);
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intel_dmc_wl_put(display, reg);
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return ret;
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}
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#define intel_de_wait_custom(p,...) __intel_de_wait_custom(__to_intel_display(p), __VA_ARGS__)
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static inline int
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__intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
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u32 mask, unsigned int timeout)
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{
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return intel_de_wait(display, reg, mask, mask, timeout);
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}
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#define intel_de_wait_for_set(p,...) __intel_de_wait_for_set(__to_intel_display(p), __VA_ARGS__)
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static inline int
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__intel_de_wait_for_clear(struct intel_display *display, i915_reg_t reg,
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u32 mask, unsigned int timeout)
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{
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return intel_de_wait(display, reg, mask, 0, timeout);
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}
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#define intel_de_wait_for_clear(p,...) __intel_de_wait_for_clear(__to_intel_display(p), __VA_ARGS__)
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/*
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* Unlocked mmio-accessors, think carefully before using these.
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*
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* Certain architectures will die if the same cacheline is concurrently accessed
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* by different clients (e.g. on Ivybridge). Access to registers should
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* therefore generally be serialised, by either the dev_priv->uncore.lock or
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* a more localised lock guarding all access to that bank of registers.
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*/
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static inline u32
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__intel_de_read_fw(struct intel_display *display, i915_reg_t reg)
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{
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u32 val;
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val = intel_uncore_read_fw(__to_uncore(display), reg);
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trace_i915_reg_rw(false, reg, val, sizeof(val), true);
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return val;
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}
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#define intel_de_read_fw(p,...) __intel_de_read_fw(__to_intel_display(p), __VA_ARGS__)
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static inline void
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__intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
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{
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trace_i915_reg_rw(true, reg, val, sizeof(val), true);
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intel_uncore_write_fw(__to_uncore(display), reg, val);
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}
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#define intel_de_write_fw(p,...) __intel_de_write_fw(__to_intel_display(p), __VA_ARGS__)
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static inline u32
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__intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
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{
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return intel_uncore_read_notrace(__to_uncore(display), reg);
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}
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#define intel_de_read_notrace(p,...) __intel_de_read_notrace(__to_intel_display(p), __VA_ARGS__)
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static inline void
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__intel_de_write_notrace(struct intel_display *display, i915_reg_t reg,
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u32 val)
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{
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intel_uncore_write_notrace(__to_uncore(display), reg, val);
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}
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#define intel_de_write_notrace(p,...) __intel_de_write_notrace(__to_intel_display(p), __VA_ARGS__)
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static __always_inline void
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intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
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i915_reg_t reg, u32 val)
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{
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if (dsb)
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intel_dsb_reg_write(dsb, reg, val);
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else
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intel_de_write_fw(display, reg, val);
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}
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#endif /* __INTEL_DE_H__ */
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