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The H5 SoC has a MBUS very similar to the H3 SoC, but it has a smaller MDFS divider range (1-4 instead of 1-16). Add a separate compatible for this variant. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211118031841.42315-4-samuel@sholland.org
159 lines
3.4 KiB
YAML
159 lines
3.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner Memory Bus (MBUS) controller
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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description: |
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The MBUS controller drives the MBUS that other devices in the SoC
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will use to perform DMA. It also has a register interface that
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allows to monitor and control the bandwidth and priorities for
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masters on that bus.
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Each device having to perform their DMA through the MBUS must have
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the interconnects and interconnect-names properties set to the MBUS
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controller and with "dma-mem" as the interconnect name.
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properties:
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"#interconnect-cells":
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const: 1
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description:
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The content of the cell is the MBUS ID.
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compatible:
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enum:
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- allwinner,sun5i-a13-mbus
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- allwinner,sun8i-h3-mbus
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- allwinner,sun8i-r40-mbus
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- allwinner,sun50i-a64-mbus
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- allwinner,sun50i-h5-mbus
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reg:
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minItems: 1
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items:
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- description: MBUS interconnect/bandwidth limit/PMU registers
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- description: DRAM controller/PHY registers
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reg-names:
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minItems: 1
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items:
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- const: mbus
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- const: dram
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clocks:
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minItems: 1
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items:
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- description: MBUS interconnect module clock
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- description: DRAM controller/PHY module clock
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- description: Register bus clock, shared by MBUS and DRAM
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clock-names:
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minItems: 1
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items:
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- const: mbus
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- const: dram
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- const: bus
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interrupts:
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maxItems: 1
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description:
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MBUS PMU activity interrupt.
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dma-ranges:
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description:
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See section 2.3.9 of the DeviceTree Specification.
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'#address-cells': true
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'#size-cells': true
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required:
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- "#interconnect-cells"
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- compatible
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- reg
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- clocks
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- dma-ranges
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if:
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properties:
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compatible:
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contains:
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enum:
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- allwinner,sun8i-h3-mbus
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- allwinner,sun50i-a64-mbus
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- allwinner,sun50i-h5-mbus
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then:
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properties:
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reg:
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minItems: 2
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reg-names:
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minItems: 2
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clocks:
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minItems: 3
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clock-names:
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minItems: 3
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required:
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- reg-names
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- clock-names
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else:
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properties:
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reg:
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maxItems: 1
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reg-names:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/sun50i-a64-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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dram-controller@1c01000 {
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compatible = "allwinner,sun5i-a13-mbus";
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reg = <0x01c01000 0x1000>;
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clocks = <&ccu CLK_MBUS>;
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#address-cells = <1>;
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#size-cells = <1>;
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dma-ranges = <0x00000000 0x40000000 0x20000000>;
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#interconnect-cells = <1>;
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};
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- |
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dram-controller@1c62000 {
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compatible = "allwinner,sun50i-a64-mbus";
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reg = <0x01c62000 0x1000>,
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<0x01c63000 0x1000>;
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reg-names = "mbus", "dram";
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clocks = <&ccu CLK_MBUS>,
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<&ccu CLK_DRAM>,
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<&ccu CLK_BUS_DRAM>;
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clock-names = "mbus", "dram", "bus";
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interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <1>;
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dma-ranges = <0x00000000 0x40000000 0xc0000000>;
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#interconnect-cells = <1>;
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};
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...
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