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The timings node maximum frequency was passed as an unit address, which is actually a workaround. Such workaround and unit address are not needed at all, because the device memory node (parent) can contain multiple timing nodes without unit addresses but with suffix used for nodenames, e.g. timings-1. LPDDR2 bindings already use such version, so unify the LPDDR3 with them. Suggested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220206135807.211767-7-krzysztof.kozlowski@canonical.com
158 lines
4.0 KiB
YAML
158 lines
4.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
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maintainers:
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- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
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properties:
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compatible:
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const: jedec,lpddr3-timings
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reg:
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maxItems: 1
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description: |
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Maximum DDR clock frequency for the speed-bin, in Hz.
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Property is deprecated, use max-freq.
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deprecated: true
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max-freq:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Maximum DDR clock frequency for the speed-bin, in Hz.
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min-freq:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Minimum DDR clock frequency for the speed-bin, in Hz.
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tCKE:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.
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tCKESR:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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CKE minimum pulse width during SELF REFRESH (low pulse width during
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SELF REFRESH) in pico seconds.
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tFAW:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Four-bank activate window in pico seconds.
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tMRD:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Mode register set command delay in pico seconds.
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tR2R-C2C:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Additional READ-to-READ delay in chip-to-chip cases in pico seconds.
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tRAS:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Row active time in pico seconds.
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tRC:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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ACTIVATE-to-ACTIVATE command period in pico seconds.
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tRCD:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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RAS-to-CAS delay in pico seconds.
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tRFC:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Refresh Cycle time in pico seconds.
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tRPab:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Row precharge time (all banks) in pico seconds.
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tRPpb:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Row precharge time (single banks) in pico seconds.
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tRRD:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Active bank A to active bank B in pico seconds.
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tRTP:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Internal READ to PRECHARGE command delay in pico seconds.
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tW2W-C2C:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.
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tWR:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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WRITE recovery time in pico seconds.
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tWTR:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Internal WRITE-to-READ command delay in pico seconds.
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tXP:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Exit power-down to next valid command delay in pico seconds.
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tXSR:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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SELF REFRESH exit to next valid command delay in pico seconds.
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required:
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- compatible
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- min-freq
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- max-freq
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additionalProperties: false
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examples:
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- |
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lpddr3 {
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timings {
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compatible = "jedec,lpddr3-timings";
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max-freq = <800000000>;
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min-freq = <100000000>;
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tCKE = <3750>;
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tCKESR = <3750>;
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tFAW = <25000>;
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tMRD = <7000>;
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tR2R-C2C = <0>;
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tRAS = <23000>;
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tRC = <33750>;
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tRCD = <10000>;
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tRFC = <65000>;
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tRPab = <12000>;
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tRPpb = <12000>;
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tRRD = <6000>;
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tRTP = <3750>;
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tW2W-C2C = <0>;
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tWR = <7500>;
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tWTR = <3750>;
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tXP = <3750>;
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tXSR = <70000>;
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};
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};
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