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The Xilinx QSPI controller has two advanced modes which allow the controller to behave differently and consider two flashes as one single storage. One of these two modes is quite complex to support from a binding point of view and is the dual parallel memories. In this mode, each byte of data is stored in both devices: the even bits in one, the odd bits in the other. The split is automatically handled by the QSPI controller and is transparent for the user. The other mode is simpler to support, it is called dual stacked memories. The controller shares the same SPI bus but each of the devices contain half of the data. Once in this mode, the controller does not follow CS requests but instead internally wires the two CS levels with the value of the most significant address bit. Supporting these two modes will involve core changes which include the possibility of providing two CS for a single SPI device Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220126112608.955728-2-miquel.raynal@bootlin.com Signed-off-by: Mark Brown <broonie@kernel.org>
111 lines
3.2 KiB
YAML
111 lines
3.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SPI NOR flash ST M25Pxx (and similar) serial flash chips
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maintainers:
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- Rob Herring <robh@kernel.org>
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allOf:
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- $ref: "mtd.yaml#"
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- $ref: /schemas/spi/spi-peripheral-props.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- pattern: "^((((micron|spansion|st),)?\
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(m25p(40|80|16|32|64|128)|\
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n25q(32b|064|128a11|128a13|256a|512a|164k)))|\
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atmel,at25df(321a|641|081a)|\
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everspin,mr25h(10|40|128|256)|\
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(mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|\
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(mxicy|macronix),mx25u(4033|4035)|\
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(spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|\
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(sst|microchip),sst25vf(016b|032b|040b)|\
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(sst,)?sst26wf016b|\
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(sst,)?sst25wf(040b|080)|\
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winbond,w25x(80|32)|\
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(winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$"
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- const: jedec,spi-nor
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- items:
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- enum:
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- issi,is25lp016d
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- micron,mt25qu02g
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- mxicy,mx25r1635f
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- mxicy,mx25u6435f
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- mxicy,mx25v8035f
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- spansion,s25sl12801
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- spansion,s25fs512s
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- const: jedec,spi-nor
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- const: jedec,spi-nor
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description:
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Must also include "jedec,spi-nor" for any SPI NOR flash that can be
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identified by the JEDEC READ ID opcode (0x9F).
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reg:
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minItems: 1
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maxItems: 2
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spi-max-frequency: true
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spi-rx-bus-width: true
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spi-tx-bus-width: true
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m25p,fast-read:
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type: boolean
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description:
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Use the "fast read" opcode to read data from the chip instead of the usual
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"read" opcode. This opcode is not supported by all chips and support for
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it can not be detected at runtime. Refer to your chips' datasheet to check
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if this is supported by your chip.
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broken-flash-reset:
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type: boolean
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description:
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Some flash devices utilize stateful addressing modes (e.g., for 32-bit
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addressing) which need to be managed carefully by a system. Because these
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sorts of flash don't have a standardized software reset command, and
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because some systems don't toggle the flash RESET# pin upon system reset
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(if the pin even exists at all), there are systems which cannot reboot
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properly if the flash is left in the "wrong" state. This boolean flag can
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be used on such systems, to denote the absence of a reliable reset
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mechanism.
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label: true
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partitions:
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type: object
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'#address-cells': true
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'#size-cells': true
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patternProperties:
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# Note: use 'partitions' node for new users
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'^partition@':
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type: object
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"^otp(-[0-9]+)?$":
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type: object
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unevaluatedProperties: false
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examples:
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- |
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,m25p80", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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m25p,fast-read;
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};
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};
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...
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