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02a64ef64c
Add a compatible for the UART on the ARTPEC-8 SoC. This hardware block is closely related to the variants used on the Exynos chips. The register layout is identical to Exynos850 et al but the fifo size is different (64 bytes in each direction for all instances). Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220311094515.3223023-2-vincent.whitchurch@axis.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
145 lines
3.5 KiB
YAML
145 lines
3.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/serial/samsung_uart.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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description: |+
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Each Samsung UART should have an alias correctly numbered in the "aliases"
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node, according to serialN format, where N is the port number (non-negative
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decimal integer) as specified by User's Manual of respective SoC.
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properties:
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compatible:
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items:
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- enum:
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- apple,s5l-uart
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- axis,artpec8-uart
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- samsung,s3c2410-uart
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- samsung,s3c2412-uart
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- samsung,s3c2440-uart
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- samsung,s3c6400-uart
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- samsung,s5pv210-uart
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- samsung,exynos4210-uart
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- samsung,exynos5433-uart
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- samsung,exynos850-uart
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reg:
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maxItems: 1
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reg-io-width:
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description: |
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The size (in bytes) of the IO accesses that should be performed
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on the device.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 1, 4 ]
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clocks:
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minItems: 2
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maxItems: 5
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clock-names:
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description: N = 0 is allowed for SoCs without internal baud clock mux.
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minItems: 2
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items:
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- const: uart
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- pattern: '^clk_uart_baud[0-3]$'
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- pattern: '^clk_uart_baud[0-3]$'
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- pattern: '^clk_uart_baud[0-3]$'
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- pattern: '^clk_uart_baud[0-3]$'
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dmas:
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items:
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- description: DMA controller phandle and request line for RX
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- description: DMA controller phandle and request line for TX
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dma-names:
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items:
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- const: rx
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- const: tx
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interrupts:
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description: RX interrupt and optionally TX interrupt.
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minItems: 1
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maxItems: 2
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samsung,uart-fifosize:
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description: The fifo size supported by the UART channel.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [16, 64, 256]
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required:
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- compatible
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- clocks
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- clock-names
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- interrupts
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- reg
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unevaluatedProperties: false
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allOf:
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- $ref: serial.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,s3c2410-uart
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- samsung,s5pv210-uart
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 3
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clock-names:
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minItems: 2
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maxItems: 3
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items:
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- const: uart
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- pattern: '^clk_uart_baud[0-1]$'
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- pattern: '^clk_uart_baud[0-1]$'
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- if:
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properties:
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compatible:
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contains:
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enum:
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- apple,s5l-uart
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- axis,artpec8-uart
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- samsung,exynos4210-uart
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- samsung,exynos5433-uart
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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minItems: 2
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maxItems: 2
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items:
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- const: uart
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- const: clk_uart_baud0
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examples:
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- |
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#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
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uart0: serial@7f005000 {
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compatible = "samsung,s3c6400-uart";
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reg = <0x7f005000 0x100>;
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interrupt-parent = <&vic1>;
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interrupts = <5>;
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clock-names = "uart", "clk_uart_baud2",
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"clk_uart_baud3";
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clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
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<&clocks SCLK_UART>;
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samsung,uart-fifosize = <16>;
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};
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