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30424ebae8
UAPI Changes: - Weak parallel submission support for execlists Minimal implementation of the parallel submission support for execlists backend that was previously only implemented for GuC. Support one sibling non-virtual engine. Core Changes: - Two backmerges of drm/drm-next for header file renames/changes and i915_regs reorganization Driver Changes: - Add new DG2 subplatform: DG2-G12 (Matt R) - Add new DG2 workarounds (Matt R, Ram, Bruce) - Handle pre-programmed WOPCM registers for DG2+ (Daniele) - Update guc shim control programming on XeHP SDV+ (Daniele) - Add RPL-S C0/D0 stepping information (Anusha) - Improve GuC ADS initialization to work on ARM64 on dGFX (Lucas) - Fix KMD and GuC race on accessing PMU busyness (Umesh) - Use PM timestamp instead of RING TIMESTAMP for reference in PMU with GuC (Umesh) - Report error on invalid reset notification from GuC (John) - Avoid WARN splat by holding RPM wakelock during PXP unbind (Juston) - Fixes to parallel submission implementation (Matt B.) - Improve GuC loading status check/error reports (John) - Tweak TTM LRU priority hint selection (Matt A.) - Align the plane_vma to min_page_size of stolen mem (Ram) - Introduce vma resources and implement async unbinding (Thomas) - Use struct vma_resource instead of struct vma_snapshot (Thomas) - Return some TTM accel move errors instead of trying memcpy move (Thomas) - Fix a race between vma / object destruction and unbinding (Thomas) - Remove short-term pins from execbuf (Maarten) - Update to GuC version 69.0.3 (John, Michal Wa.) - Improvements to GT reset paths in GuC backend (Matt B.) - Use shrinker_release_pages instead of writeback in shmem object hooks (Matt A., Tvrtko) - Use trylock instead of blocking lock when freeing GEM objects (Maarten) - Allocate intel_engine_coredump_alloc with ALLOW_FAIL (Matt B.) - Fixes to object unmapping and purging (Matt A) - Check for wedged device in GuC backend (John) - Avoid lockdep splat by locking dpt_obj around set_cache_level (Maarten) - Allow dead vm to unbind vma's without lock (Maarten) - s/engine->i915/i915/ for DG2 engine workarounds (Matt R) - Use to_gt() helper for GGTT accesses (Michal Wi.) - Selftest improvements (Matt B., Thomas, Ram) - Coding style and compiler warning fixes (Matt B., Jasmine, Andi, Colin, Gustavo, Dan) From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/Yg4i2aCZvvee5Eai@jlahtine-mobl.ger.corp.intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> [Fixed conflicts while applying, using the fixups/drm-intel-gt-next.patch from drm-rerere's 1f2b1742abdd ("2022y-02m-23d-16h-07m-57s UTC: drm-tip rerere cache update")]
151 lines
4.8 KiB
C
151 lines
4.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2014-2019 Intel Corporation
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*/
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#ifndef _INTEL_GUC_REG_H_
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#define _INTEL_GUC_REG_H_
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include "i915_reg_defs.h"
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/* Definitions of GuC H/W registers, bits, etc */
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#define GUC_STATUS _MMIO(0xc000)
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#define GS_RESET_SHIFT 0
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#define GS_MIA_IN_RESET (0x01 << GS_RESET_SHIFT)
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#define GS_BOOTROM_SHIFT 1
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#define GS_BOOTROM_MASK (0x7F << GS_BOOTROM_SHIFT)
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#define GS_BOOTROM_RSA_FAILED (0x50 << GS_BOOTROM_SHIFT)
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#define GS_BOOTROM_JUMP_PASSED (0x76 << GS_BOOTROM_SHIFT)
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#define GS_UKERNEL_SHIFT 8
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#define GS_UKERNEL_MASK (0xFF << GS_UKERNEL_SHIFT)
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#define GS_MIA_SHIFT 16
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#define GS_MIA_MASK (0x07 << GS_MIA_SHIFT)
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#define GS_MIA_CORE_STATE (0x01 << GS_MIA_SHIFT)
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#define GS_MIA_HALT_REQUESTED (0x02 << GS_MIA_SHIFT)
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#define GS_MIA_ISR_ENTRY (0x04 << GS_MIA_SHIFT)
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#define GS_AUTH_STATUS_SHIFT 30
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#define GS_AUTH_STATUS_MASK (0x03 << GS_AUTH_STATUS_SHIFT)
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#define GS_AUTH_STATUS_BAD (0x01 << GS_AUTH_STATUS_SHIFT)
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#define GS_AUTH_STATUS_GOOD (0x02 << GS_AUTH_STATUS_SHIFT)
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#define SOFT_SCRATCH(n) _MMIO(0xc180 + (n) * 4)
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#define SOFT_SCRATCH_COUNT 16
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#define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4)
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#define GEN11_SOFT_SCRATCH_COUNT 4
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#define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4)
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#define UOS_RSA_SCRATCH_COUNT 64
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#define DMA_ADDR_0_LOW _MMIO(0xc300)
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#define DMA_ADDR_0_HIGH _MMIO(0xc304)
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#define DMA_ADDR_1_LOW _MMIO(0xc308)
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#define DMA_ADDR_1_HIGH _MMIO(0xc30c)
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#define DMA_ADDRESS_SPACE_WOPCM (7 << 16)
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#define DMA_ADDRESS_SPACE_GTT (8 << 16)
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#define DMA_COPY_SIZE _MMIO(0xc310)
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#define DMA_CTRL _MMIO(0xc314)
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#define HUC_UKERNEL (1<<9)
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#define UOS_MOVE (1<<4)
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#define START_DMA (1<<0)
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#define DMA_GUC_WOPCM_OFFSET _MMIO(0xc340)
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#define GUC_WOPCM_OFFSET_VALID (1<<0)
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#define HUC_LOADING_AGENT_VCR (0<<1)
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#define HUC_LOADING_AGENT_GUC (1<<1)
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#define GUC_WOPCM_OFFSET_SHIFT 14
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#define GUC_WOPCM_OFFSET_MASK (0x3ffff << GUC_WOPCM_OFFSET_SHIFT)
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#define GUC_MAX_IDLE_COUNT _MMIO(0xC3E4)
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#define HUC_STATUS2 _MMIO(0xD3B0)
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#define HUC_FW_VERIFIED (1<<7)
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#define GEN11_HUC_KERNEL_LOAD_INFO _MMIO(0xC1DC)
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#define HUC_LOAD_SUCCESSFUL (1 << 0)
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#define GUC_WOPCM_SIZE _MMIO(0xc050)
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#define GUC_WOPCM_SIZE_LOCKED (1<<0)
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#define GUC_WOPCM_SIZE_SHIFT 12
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#define GUC_WOPCM_SIZE_MASK (0xfffff << GUC_WOPCM_SIZE_SHIFT)
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#define GEN8_GT_PM_CONFIG _MMIO(0x138140)
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#define GEN9LP_GT_PM_CONFIG _MMIO(0x138140)
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#define GEN9_GT_PM_CONFIG _MMIO(0x13816c)
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#define GT_DOORBELL_ENABLE (1<<0)
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#define GEN8_GTCR _MMIO(0x4274)
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#define GEN8_GTCR_INVALIDATE (1<<0)
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#define GEN12_GUC_TLB_INV_CR _MMIO(0xcee8)
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#define GEN12_GUC_TLB_INV_CR_INVALIDATE (1 << 0)
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#define GUC_ARAT_C6DIS _MMIO(0xA178)
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#define GUC_SHIM_CONTROL _MMIO(0xc064)
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#define GUC_DISABLE_SRAM_INIT_TO_ZEROES (1<<0)
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#define GUC_ENABLE_READ_CACHE_LOGIC (1<<1)
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#define GUC_ENABLE_MIA_CACHING (1<<2)
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#define GUC_GEN10_MSGCH_ENABLE (1<<4)
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#define GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA (1<<9)
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#define GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA (1<<10)
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#define GUC_ENABLE_MIA_CLOCK_GATING (1<<15)
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#define GUC_GEN10_SHIM_WC_ENABLE (1<<21)
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#define GUC_SHIM_CONTROL2 _MMIO(0xc068)
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#define GUC_IS_PRIVILEGED (1<<29)
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#define GUC_SEND_INTERRUPT _MMIO(0xc4c8)
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#define GUC_SEND_TRIGGER (1<<0)
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#define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0)
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#define GUC_NUM_DOORBELLS 256
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/* format of the HW-monitored doorbell cacheline */
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struct guc_doorbell_info {
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u32 db_status;
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#define GUC_DOORBELL_DISABLED 0
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#define GUC_DOORBELL_ENABLED 1
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u32 cookie;
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u32 reserved[14];
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} __packed;
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#define GEN8_DRBREGL(x) _MMIO(0x1000 + (x) * 8)
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#define GEN8_DRB_VALID (1<<0)
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#define GEN8_DRBREGU(x) _MMIO(0x1000 + (x) * 8 + 4)
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#define GEN12_DIST_DBS_POPULATED _MMIO(0xd08)
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#define GEN12_DOORBELLS_PER_SQIDI_SHIFT 16
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#define GEN12_DOORBELLS_PER_SQIDI (0xff)
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#define GEN12_SQIDIS_DOORBELL_EXIST (0xffff)
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#define DE_GUCRMR _MMIO(0x44054)
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#define GUC_BCS_RCS_IER _MMIO(0xC550)
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#define GUC_VCS2_VCS1_IER _MMIO(0xC554)
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#define GUC_WD_VECS_IER _MMIO(0xC558)
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#define GUC_PM_P24C_IER _MMIO(0xC55C)
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/* GuC Interrupt Vector */
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#define GUC_INTR_GUC2HOST BIT(15)
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#define GUC_INTR_EXEC_ERROR BIT(14)
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#define GUC_INTR_DISPLAY_EVENT BIT(13)
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#define GUC_INTR_SEM_SIG BIT(12)
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#define GUC_INTR_IOMMU2GUC BIT(11)
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#define GUC_INTR_DOORBELL_RANG BIT(10)
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#define GUC_INTR_DMA_DONE BIT(9)
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#define GUC_INTR_FATAL_ERROR BIT(8)
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#define GUC_INTR_NOTIF_ERROR BIT(7)
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#define GUC_INTR_SW_INT_6 BIT(6)
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#define GUC_INTR_SW_INT_5 BIT(5)
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#define GUC_INTR_SW_INT_4 BIT(4)
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#define GUC_INTR_SW_INT_3 BIT(3)
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#define GUC_INTR_SW_INT_2 BIT(2)
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#define GUC_INTR_SW_INT_1 BIT(1)
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#define GUC_INTR_SW_INT_0 BIT(0)
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#endif
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