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ece3c31981
Clean the Qualcomm SoCs clock bindings: 1. Drop redundant "bindings" in title. 2. Correct language grammar "<independent clause without verb>, which supports" -> "provides". 3. Use full path to the bindings header, so tools can validate it. 4. Drop quotes where not needed. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com> # msm8998 Acked-by: Jeffrey Hugo <quic_jhugo@quicinc.com> # mmcc Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221102163153.55460-2-krzysztof.kozlowski@linaro.org
67 lines
1.8 KiB
YAML
67 lines
1.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Global Clock & Reset Controller on SDX65
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maintainers:
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- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
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description: |
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Qualcomm global clock control module provides the clocks, resets and power
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domains on SDX65
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See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h
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properties:
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compatible:
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const: qcom,gcc-sdx65
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clocks:
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items:
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- description: Board XO source
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- description: Board active XO source
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- description: Sleep clock source
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- description: PCIE Pipe clock source
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- description: USB3 phy wrapper pipe clock source
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- description: PLL test clock source (Optional clock)
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minItems: 5
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clock-names:
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items:
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- const: bi_tcxo
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- const: bi_tcxo_ao
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- const: sleep_clk
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- const: pcie_pipe_clk
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- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
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- const: core_bi_pll_test_se # Optional clock
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minItems: 5
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required:
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- compatible
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- clocks
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- clock-names
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allOf:
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- $ref: qcom,gcc.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@100000 {
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compatible = "qcom,gcc-sdx65";
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reg = <0x100000 0x1f7400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
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<&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>;
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clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
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"pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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