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687daae794
Convert the TI CDCE925 clock binding to DT schema format. Including a small fix: Add the missing 'ti' prefix in the example compatible. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/20221021064757.379558-1-alexander.stein@ew.tq-group.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
104 lines
2.6 KiB
YAML
104 lines
2.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/ti,cdce925.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI CDCE913/925/937/949 programmable I2C clock synthesizers
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maintainers:
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- Alexander Stein <alexander.stein@ew.tq-group.com>
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description: |
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Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction
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- CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
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- CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
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- CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
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- CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
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properties:
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compatible:
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enum:
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- ti,cdce913
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- ti,cdce925
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- ti,cdce937
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- ti,cdce949
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reg:
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maxItems: 1
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clocks:
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items:
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- description: fixed parent clock
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"#clock-cells":
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const: 1
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vdd-supply:
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description: Regulator that provides 1.8V Vdd power supply
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vddout-supply:
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description: |
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Regulator that provides Vddout power supply.
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non-L variant: 2.5V or 3.3V for
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L variant: 1.8V for
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xtal-load-pf:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Crystal load-capacitor value to fine-tune performance on a
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board, or to compensate for external influences.
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patternProperties:
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"^PLL[1-4]$":
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type: object
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description: |
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optional child node can be used to specify spread
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spectrum clocking parameters for a board
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additionalProperties: false
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properties:
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spread-spectrum:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: SSC mode as defined in the data sheet
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spread-spectrum-center:
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type: boolean
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description: |
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Use "centered" mode instead of "max" mode. When
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present, the clock runs at the requested frequency on average.
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Otherwise the requested frequency is the maximum value of the
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SCC range.
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required:
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- compatible
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- reg
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- clocks
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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cdce925: clock-controller@64 {
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compatible = "ti,cdce925";
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reg = <0x64>;
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clocks = <&xtal_27Mhz>;
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#clock-cells = <1>;
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xtal-load-pf = <5>;
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vdd-supply = <®_1v8>;
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vddout-supply = <®_3v3>;
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/* PLL options to get SSC 1% centered */
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PLL2 {
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spread-spectrum = <4>;
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spread-spectrum-center;
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};
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};
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};
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