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c54155622c
Adding in msm8939 which is based msm8916 dtsi I stumbled across a binding check complaining about the phy name for msm8916 which we were reusing for msm8939. The currently inconsistent upstream dtsi naming of "dsi" and "dsi-phy" is not captured in the yaml for this driver. The driver however doesn't care about the name of DSI phy, hence the yaml check is redundant. Both Krzysztof and Rob suggested we could drop the phy-names entirely if it really isn't a dependency. So, drop the inconsistent and unnecessary phy-names field from the yaml. Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
207 lines
5.0 KiB
YAML
207 lines
5.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display DSI controller
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maintainers:
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- Krishna Manikandan <quic_mkrishn@quicinc.com>
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allOf:
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- $ref: "../dsi-controller.yaml#"
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properties:
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compatible:
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enum:
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- qcom,mdss-dsi-ctrl
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- qcom,dsi-ctrl-6g-qcm2290
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reg:
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maxItems: 1
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reg-names:
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const: dsi_ctrl
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Display byte clock
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- description: Display byte interface clock
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- description: Display pixel clock
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- description: Display escape clock
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- description: Display AHB clock
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- description: Display AXI clock
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clock-names:
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items:
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- const: byte
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- const: byte_intf
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- const: pixel
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- const: core
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- const: iface
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- const: bus
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phys:
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maxItems: 1
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phy-names:
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deprecated: true
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const: dsi
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"#address-cells": true
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"#size-cells": true
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syscon-sfpb:
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description: A phandle to mmss_sfpb syscon node (only for DSIv2).
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$ref: "/schemas/types.yaml#/definitions/phandle"
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qcom,dual-dsi-mode:
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type: boolean
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description: |
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Indicates if the DSI controller is driving a panel which needs
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2 DSI links.
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assigned-clocks:
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maxItems: 2
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description: |
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Parents of "byte" and "pixel" for the given platform.
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assigned-clock-parents:
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maxItems: 2
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description: |
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The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
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power-domains:
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maxItems: 1
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operating-points-v2: true
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opp-table:
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type: object
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ports:
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$ref: "/schemas/graph.yaml#/properties/ports"
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description: |
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Contains DSI controller input and output ports as children, each
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containing one endpoint subnode.
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properties:
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port@0:
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$ref: "/schemas/graph.yaml#/$defs/port-base"
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unevaluatedProperties: false
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description: |
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Input endpoints of the controller.
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properties:
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endpoint:
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$ref: /schemas/media/video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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maxItems: 4
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minItems: 4
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items:
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enum: [ 0, 1, 2, 3 ]
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port@1:
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$ref: "/schemas/graph.yaml#/$defs/port-base"
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unevaluatedProperties: false
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description: |
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Output endpoints of the controller.
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properties:
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endpoint:
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$ref: /schemas/media/video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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maxItems: 4
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minItems: 4
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items:
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enum: [ 0, 1, 2, 3 ]
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- clocks
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- clock-names
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- phys
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- assigned-clocks
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- assigned-clock-parents
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- power-domains
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- operating-points-v2
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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dsi@ae94000 {
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compatible = "qcom,mdss-dsi-ctrl";
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reg = <0x0ae94000 0x400>;
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reg-names = "dsi_ctrl";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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phys = <&dsi0_phy>;
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phy-names = "dsi";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
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assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
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power-domains = <&rpmhpd SC7180_CX>;
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operating-points-v2 = <&dsi_opp_table>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_out: endpoint {
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remote-endpoint = <&sn65dsi86_in>;
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data-lanes = <0 1 2 3>;
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};
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};
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};
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};
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...
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