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Fixed string node names should be under 'properties' rather than 'patternProperties'. Additionally, without beginning and end of line anchors, any prefix or suffix is allowed on the specified node name. These cases don't appear to want a prefix or suffix, so move them under 'properties'. In some cases, the diff turns out to look like we're moving some patterns rather than the fixed string properties. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20221118223708.1721134-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
210 lines
7.1 KiB
YAML
210 lines
7.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
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# Copyright (C) 2019 Texas Instruments Incorporated
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/tlv320adcx140.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
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maintainers:
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- Andrew Davis <afd@ti.com>
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description: |
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The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
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PDM microphones recording), high-performance audio, analog-to-digital
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converter (ADC) with analog inputs supporting up to 2V RMS. The TLV320ADCX140
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family supports line and microphone Inputs, and offers a programmable
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microphone bias or supply voltage generation.
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Specifications can be found at:
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https://www.ti.com/lit/ds/symlink/tlv320adc3140.pdf
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https://www.ti.com/lit/ds/symlink/tlv320adc5140.pdf
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https://www.ti.com/lit/ds/symlink/tlv320adc6140.pdf
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properties:
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compatible:
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enum:
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- ti,tlv320adc3140
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- ti,tlv320adc5140
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- ti,tlv320adc6140
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reg:
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maxItems: 1
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description: |
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I2C addresss of the device can be one of these 0x4c, 0x4d, 0x4e or 0x4f
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reset-gpios:
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maxItems: 1
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description: |
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GPIO used for hardware reset.
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areg-supply:
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description: |
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Regulator with AVDD at 3.3V. If not defined then the internal regulator
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is enabled.
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ti,mic-bias-source:
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description: |
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Indicates the source for MIC Bias.
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0 - Mic bias is set to VREF
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1 - Mic bias is set to VREF × 1.096
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6 - Mic bias is set to AVDD
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 6]
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ti,vref-source:
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description: |
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Indicates the source for MIC Bias.
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0 - Set VREF to 2.75V
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1 - Set VREF to 2.5V
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2 - Set VREF to 1.375V
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2]
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ti,pdm-edge-select:
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description: |
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Defines the PDMCLK sampling edge configuration for the PDM inputs. This
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array is defined as <PDMIN1 PDMIN2 PDMIN3 PDMIN4>.
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0 - (default) Odd channel is latched on the negative edge and even
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channel is latched on the positive edge.
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1 - Odd channel is latched on the positive edge and even channel is
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latched on the negative edge.
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PDMIN1 - PDMCLK latching edge used for channel 1 and 2 data
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PDMIN2 - PDMCLK latching edge used for channel 3 and 4 data
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PDMIN3 - PDMCLK latching edge used for channel 5 and 6 data
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PDMIN4 - PDMCLK latching edge used for channel 7 and 8 data
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 4
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items:
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maximum: 1
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default: [0, 0, 0, 0]
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ti,gpi-config:
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description: |
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Defines the configuration for the general purpose input pins (GPI).
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The array is defined as <GPI1 GPI2 GPI3 GPI4>.
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0 - (default) disabled
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1 - GPIX is configured as a general-purpose input (GPI)
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2 - GPIX is configured as a master clock input (MCLK)
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3 - GPIX is configured as an ASI input for daisy-chain (SDIN)
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4 - GPIX is configured as a PDM data input for channel 1 and channel
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(PDMDIN1)
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5 - GPIX is configured as a PDM data input for channel 3 and channel
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(PDMDIN2)
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6 - GPIX is configured as a PDM data input for channel 5 and channel
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(PDMDIN3)
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7 - GPIX is configured as a PDM data input for channel 7 and channel
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(PDMDIN4)
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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maxItems: 4
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items:
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maximum: 7
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default: [0, 0, 0, 0]
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ti,gpio-config:
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description: |
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Defines the configuration and output drive for the General Purpose
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Input and Output pin (GPIO1). Its value is a pair, the first value is for
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the configuration type and the second value is for the output drive
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type. The array is defined as <GPIO1_CFG GPIO1_DRV>
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configuration for the GPIO pin can be one of the following:
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0 - disabled
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1 - GPIO1 is configured as a general-purpose output (GPO)
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2 - (default) GPIO1 is configured as a device interrupt output (IRQ)
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3 - GPIO1 is configured as a secondary ASI output (SDOUT2)
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4 - GPIO1 is configured as a PDM clock output (PDMCLK)
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8 - GPIO1 is configured as an input to control when MICBIAS turns on or
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off (MICBIAS_EN)
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9 - GPIO1 is configured as a general-purpose input (GPI)
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10 - GPIO1 is configured as a master clock input (MCLK)
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11 - GPIO1 is configured as an ASI input for daisy-chain (SDIN)
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12 - GPIO1 is configured as a PDM data input for channel 1 and channel 2
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(PDMDIN1)
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13 - GPIO1 is configured as a PDM data input for channel 3 and channel 4
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(PDMDIN2)
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14 - GPIO1 is configured as a PDM data input for channel 5 and channel 6
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(PDMDIN3)
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15 - GPIO1 is configured as a PDM data input for channel 7 and channel 8
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(PDMDIN4)
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output drive type for the GPIO pin can be one of the following:
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0 - Hi-Z output
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1 - Drive active low and active high
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2 - (default) Drive active low and weak high
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3 - Drive active low and Hi-Z
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4 - Drive weak low and active high
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5 - Drive Hi-Z and active high
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 2
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maxItems: 2
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items:
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maximum: 15
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default: [2, 2]
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ti,asi-tx-drive:
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type: boolean
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description: |
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When set the device will set the Tx ASI output to a Hi-Z state for unused
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data cycles. Default is to drive the output low on unused ASI cycles.
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patternProperties:
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'^ti,gpo-config-[1-4]$':
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: |
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Defines the configuration and output driver for the general purpose
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output pins (GPO). These values are pairs, the first value is for the
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configuration type and the second value is for the output drive type.
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The array is defined as <GPO_CFG GPO_DRV>
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GPO output configuration can be one of the following:
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0 - (default) disabled
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1 - GPOX is configured as a general-purpose output (GPO)
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2 - GPOX is configured as a device interrupt output (IRQ)
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3 - GPOX is configured as a secondary ASI output (SDOUT2)
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4 - GPOX is configured as a PDM clock output (PDMCLK)
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GPO output drive configuration for the GPO pins can be one of the following:
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0d - (default) Hi-Z output
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1d - Drive active low and active high
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2d - Drive active low and weak high
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3d - Drive active low and Hi-Z
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4d - Drive weak low and active high
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5d - Drive Hi-Z and active high
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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i2c0 {
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#address-cells = <1>;
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#size-cells = <0>;
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codec: codec@4c {
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compatible = "ti,tlv320adc5140";
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reg = <0x4c>;
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ti,mic-bias-source = <6>;
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ti,pdm-edge-select = <0 1 0 1>;
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ti,gpi-config = <4 5 6 7>;
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ti,gpio-config = <10 2>;
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ti,gpo-config-1 = <0 0>;
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ti,gpo-config-2 = <0 0>;
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reset-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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};
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};
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