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1b0b90bde6
With 'unevaluatedProperties' support implemented, the ti,rti-wdt example
has the following warning:
/home/rob/proj/git/linux-dt/.build-arm64/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.example.dt.yaml: watchdog@2200000: Unevaluated properties are not allowed ('assigned-clock-parents' was unexpected)
The problem is the schema has a typo in 'assigned-clocks-parents'. As
it is not required to list assigned clocks in bindings, just drop the
property definitions to fix this.
Cc: Wim Van Sebroeck <wim@linux-watchdog.org>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: linux-watchdog@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20211206174028.2294330-1-robh@kernel.org
62 lines
1.5 KiB
YAML
62 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/watchdog/ti,rti-wdt.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments K3 SoC Watchdog Timer
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maintainers:
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- Tero Kristo <t-kristo@ti.com>
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description:
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The TI K3 SoC watchdog timer is implemented via the RTI (Real Time
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Interrupt) IP module. This timer adds a support for windowed watchdog
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mode, which will signal an error if it is pinged outside the watchdog
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time window, meaning either too early or too late. The error signal
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generated can be routed to either interrupt a safety controller or
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to directly reset the SoC.
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allOf:
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- $ref: "watchdog.yaml#"
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properties:
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compatible:
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enum:
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- ti,j7-rti-wdt
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- power-domains
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unevaluatedProperties: false
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examples:
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- |
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/*
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* RTI WDT in main domain on J721e SoC. Assigned clocks are used to
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* select the source clock for the watchdog, forcing it to tick with
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* a 32kHz clock in this case.
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*/
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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watchdog@2200000 {
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compatible = "ti,j7-rti-wdt";
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reg = <0x2200000 0x100>;
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clocks = <&k3_clks 252 1>;
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power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
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assigned-clocks = <&k3_clks 252 1>;
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assigned-clock-parents = <&k3_clks 252 5>;
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};
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