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1198ae56c9
Add infrastructure for implementing the acomp APIs in the QAT driver and expose the deflate algorithm for QAT GEN2 devices. This adds (1) the compression service which includes logic to create, allocate and handle compression instances; (2) logic to create configuration entries at probe time for the compression instances; (3) updates to the firmware API for allowing the compression service; and; (4) a back-end for deflate that implements the acomp api for QAT GEN2 devices. The implementation configures the device to produce data compressed statically, optimized for throughput over compression ratio. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Adam Guerin <adam.guerin@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
103 lines
2.9 KiB
C
103 lines
2.9 KiB
C
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
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/* Copyright(c) 2015 - 2021 Intel Corporation */
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#include <adf_accel_devices.h>
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#include <adf_common_drv.h>
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#include <adf_gen2_config.h>
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#include <adf_gen2_dc.h>
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#include <adf_gen2_hw_data.h>
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#include <adf_gen2_pfvf.h>
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#include <adf_pfvf_vf_msg.h>
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#include "adf_c62xvf_hw_data.h"
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static struct adf_hw_device_class c62xiov_class = {
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.name = ADF_C62XVF_DEVICE_NAME,
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.type = DEV_C62XVF,
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.instances = 0
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};
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static u32 get_accel_mask(struct adf_hw_device_data *self)
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{
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return ADF_C62XIOV_ACCELERATORS_MASK;
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}
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static u32 get_ae_mask(struct adf_hw_device_data *self)
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{
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return ADF_C62XIOV_ACCELENGINES_MASK;
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}
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static u32 get_num_accels(struct adf_hw_device_data *self)
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{
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return ADF_C62XIOV_MAX_ACCELERATORS;
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}
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static u32 get_num_aes(struct adf_hw_device_data *self)
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{
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return ADF_C62XIOV_MAX_ACCELENGINES;
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}
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static u32 get_misc_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_C62XIOV_PMISC_BAR;
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}
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static u32 get_etr_bar_id(struct adf_hw_device_data *self)
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{
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return ADF_C62XIOV_ETR_BAR;
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}
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static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
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{
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return DEV_SKU_VF;
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}
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static int adf_vf_int_noop(struct adf_accel_dev *accel_dev)
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{
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return 0;
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}
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static void adf_vf_void_noop(struct adf_accel_dev *accel_dev)
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{
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}
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void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data)
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{
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hw_data->dev_class = &c62xiov_class;
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hw_data->num_banks = ADF_C62XIOV_ETR_MAX_BANKS;
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hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
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hw_data->num_accel = ADF_C62XIOV_MAX_ACCELERATORS;
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hw_data->num_logical_accel = 1;
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hw_data->num_engines = ADF_C62XIOV_MAX_ACCELENGINES;
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hw_data->tx_rx_gap = ADF_C62XIOV_RX_RINGS_OFFSET;
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hw_data->tx_rings_mask = ADF_C62XIOV_TX_RINGS_MASK;
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hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
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hw_data->alloc_irq = adf_vf_isr_resource_alloc;
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hw_data->free_irq = adf_vf_isr_resource_free;
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hw_data->enable_error_correction = adf_vf_void_noop;
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hw_data->init_admin_comms = adf_vf_int_noop;
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hw_data->exit_admin_comms = adf_vf_void_noop;
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hw_data->send_admin_init = adf_vf2pf_notify_init;
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hw_data->init_arb = adf_vf_int_noop;
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hw_data->exit_arb = adf_vf_void_noop;
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hw_data->disable_iov = adf_vf2pf_notify_shutdown;
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hw_data->get_accel_mask = get_accel_mask;
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hw_data->get_ae_mask = get_ae_mask;
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hw_data->get_num_accels = get_num_accels;
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hw_data->get_num_aes = get_num_aes;
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hw_data->get_etr_bar_id = get_etr_bar_id;
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hw_data->get_misc_bar_id = get_misc_bar_id;
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hw_data->get_sku = get_sku;
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hw_data->enable_ints = adf_vf_void_noop;
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hw_data->dev_class->instances++;
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hw_data->dev_config = adf_gen2_dev_config;
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adf_devmgr_update_class_index(hw_data);
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adf_gen2_init_vf_pfvf_ops(&hw_data->pfvf_ops);
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adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
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adf_gen2_init_dc_ops(&hw_data->dc_ops);
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}
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void adf_clean_hw_data_c62xiov(struct adf_hw_device_data *hw_data)
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{
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hw_data->dev_class->instances--;
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adf_devmgr_update_class_index(hw_data);
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}
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