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1198ae56c9
Add infrastructure for implementing the acomp APIs in the QAT driver and expose the deflate algorithm for QAT GEN2 devices. This adds (1) the compression service which includes logic to create, allocate and handle compression instances; (2) logic to create configuration entries at probe time for the compression instances; (3) updates to the firmware API for allowing the compression service; and; (4) a back-end for deflate that implements the acomp api for QAT GEN2 devices. The implementation configures the device to produce data compressed statically, optimized for throughput over compression ratio. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Wojciech Ziemba <wojciech.ziemba@intel.com> Reviewed-by: Adam Guerin <adam.guerin@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
71 lines
3.0 KiB
C
71 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright(c) 2022 Intel Corporation */
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#include "adf_accel_devices.h"
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#include "adf_gen2_dc.h"
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#include "icp_qat_fw_comp.h"
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static void qat_comp_build_deflate_ctx(void *ctx)
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{
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struct icp_qat_fw_comp_req *req_tmpl = (struct icp_qat_fw_comp_req *)ctx;
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struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr;
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struct icp_qat_fw_comp_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars;
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struct icp_qat_fw_comp_req_params *req_pars = &req_tmpl->comp_pars;
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struct icp_qat_fw_comp_cd_hdr *comp_cd_ctrl = &req_tmpl->comp_cd_ctrl;
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memset(req_tmpl, 0, sizeof(*req_tmpl));
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header->hdr_flags =
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ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
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header->service_type = ICP_QAT_FW_COMN_REQ_CPM_FW_COMP;
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header->service_cmd_id = ICP_QAT_FW_COMP_CMD_STATIC;
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header->comn_req_flags =
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ICP_QAT_FW_COMN_FLAGS_BUILD(QAT_COMN_CD_FLD_TYPE_16BYTE_DATA,
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QAT_COMN_PTR_TYPE_SGL);
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header->serv_specif_flags =
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ICP_QAT_FW_COMP_FLAGS_BUILD(ICP_QAT_FW_COMP_STATELESS_SESSION,
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ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST,
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ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST,
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ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST,
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ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF);
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cd_pars->u.sl.comp_slice_cfg_word[0] =
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ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(ICP_QAT_HW_COMPRESSION_DIR_COMPRESS,
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ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED,
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ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE,
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ICP_QAT_HW_COMPRESSION_DEPTH_1,
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ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
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req_pars->crc.legacy.initial_adler = COMP_CPR_INITIAL_ADLER;
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req_pars->crc.legacy.initial_crc32 = COMP_CPR_INITIAL_CRC;
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req_pars->req_par_flags =
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ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(ICP_QAT_FW_COMP_SOP,
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ICP_QAT_FW_COMP_EOP,
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ICP_QAT_FW_COMP_BFINAL,
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ICP_QAT_FW_COMP_CNV,
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ICP_QAT_FW_COMP_CNV_RECOVERY,
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ICP_QAT_FW_COMP_NO_CNV_DFX,
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ICP_QAT_FW_COMP_CRC_MODE_LEGACY,
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ICP_QAT_FW_COMP_NO_XXHASH_ACC,
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ICP_QAT_FW_COMP_CNV_ERROR_NONE,
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ICP_QAT_FW_COMP_NO_APPEND_CRC,
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ICP_QAT_FW_COMP_NO_DROP_DATA);
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ICP_QAT_FW_COMN_NEXT_ID_SET(comp_cd_ctrl, ICP_QAT_FW_SLICE_DRAM_WR);
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ICP_QAT_FW_COMN_CURR_ID_SET(comp_cd_ctrl, ICP_QAT_FW_SLICE_COMP);
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/* Fill second half of the template for decompression */
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memcpy(req_tmpl + 1, req_tmpl, sizeof(*req_tmpl));
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req_tmpl++;
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header = &req_tmpl->comn_hdr;
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header->service_cmd_id = ICP_QAT_FW_COMP_CMD_DECOMPRESS;
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cd_pars = &req_tmpl->cd_pars;
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cd_pars->u.sl.comp_slice_cfg_word[0] =
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ICP_QAT_HW_COMPRESSION_CONFIG_BUILD(ICP_QAT_HW_COMPRESSION_DIR_DECOMPRESS,
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ICP_QAT_HW_COMPRESSION_DELAYED_MATCH_DISABLED,
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ICP_QAT_HW_COMPRESSION_ALGO_DEFLATE,
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ICP_QAT_HW_COMPRESSION_DEPTH_1,
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ICP_QAT_HW_COMPRESSION_FILE_TYPE_0);
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}
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void adf_gen2_init_dc_ops(struct adf_dc_ops *dc_ops)
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{
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dc_ops->build_deflate_ctx = qat_comp_build_deflate_ctx;
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}
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EXPORT_SYMBOL_GPL(adf_gen2_init_dc_ops);
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