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f60a2abfdb
Pull clk updates from Stephen Boyd: "The diff is dominated by the Allwinner A10/A20 SoCs getting converted to the sunxi-ng framework. Otherwise, the heavy hitters are various drivers for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are some other new clk drivers in here too but overall this is just a bunch of clk drivers for various different pieces of hardware and a collection of non-critical fixes for clk drivers. New Drivers: - Allwinner R40 SoCs - Renesas R-Car Gen3 USB 2.0 clock selector PHY - Atmel AT91 audio PLL - Uniphier PXs3 SoCs - ARC HSDK Board PLLs - AXS10X Board PLLs - STMicroelectronics STM32H743 SoCs Removed Drivers: - Non-compiling mb86s7x support Updates: - Allwinner A10/A20 SoCs converted to sunxi-ng framework - Allwinner H3 CPU clk fixes - Renesas R-Car D3 SoC - Renesas V2H and M3-W modules - Samsung Exynos5420/5422/5800 audio fixes - Rockchip fractional clk approximation fixes - Rockchip rk3126 SoC support within the rk3128 driver - Amlogic gxbb CEC32 and sd_emmc clks - Amlogic meson8b reset controller support - IDT VersaClock 5P49V5925/5P49V6901 support - Qualcomm MSM8996 SMMU clks - Various 'const' applications for struct clk_ops - si5351 PLL reset bugfix - Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2 - Assorted Tegra clk driver fixes" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (120 commits) clk: si5351: fix PLL reset ASoC: atmel-classd: remove aclk clock ASoC: atmel-classd: remove aclk clock from DT binding clk: at91: clk-generated: make gclk determine audio_pll rate clk: at91: clk-generated: create function to find best_diff clk: at91: add audio pll clock drivers dt-bindings: clk: at91: add audio plls to the compatible list clk: at91: clk-generated: remove useless divisor loop clk: mb86s7x: Drop non-building driver clk: ti: check for null return in strrchr to avoid null dereferencing clk: Don't write error code into divider register clk: uniphier: add video input subsystem clock clk: uniphier: add audio system clock clk: stm32h7: Add stm32h743 clock driver clk: gate: expose clk_gate_ops::is_enabled clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled() clk: uniphier: add PXs3 clock data clk: hi6220: change watchdog clock source clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808 clk: cs2000: Add cs2000_set_saved_rate ...
55 lines
1.8 KiB
Plaintext
55 lines
1.8 KiB
Plaintext
* Amlogic GXBB AO Clock and Reset Unit
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The Amlogic GXBB AO clock controller generates and supplies clock to various
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controllers within the Always-On part of the SoC.
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Required Properties:
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- compatible: value should be different for each SoC family as :
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- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
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- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
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- GXM (S912) : "amlogic,meson-gxm-aoclkc"
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followed by the common "amlogic,meson-gx-aoclkc"
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
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used in device tree sources.
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- #reset-cells: should be 1.
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Each reset is assigned an identifier and client nodes can use this identifier
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to specify the reset which they consume. All available resets are defined as
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preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
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used in device tree sources.
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Parent node should have the following properties :
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- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
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- reg: base address and size of the AO system control register space.
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Example: AO Clock controller node:
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ao_sysctrl: sys-ctrl@0 {
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compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
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reg = <0x0 0x0 0x0 0x100>;
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clkc_AO: clock-controller {
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compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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};
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Example: UART controller node that consumes the clock and reset generated
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by the clock controller:
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uart_AO: serial@4c0 {
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compatible = "amlogic,meson-uart";
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reg = <0x4c0 0x14>;
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interrupts = <0 90 1>;
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clocks = <&clkc_AO CLKID_AO_UART1>;
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resets = <&clkc_AO RESET_AO_UART1>;
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};
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