mirror of
https://github.com/torvalds/linux.git
synced 2026-04-21 16:23:59 -04:00
e60e1ee606
Pull drm updates from Dave Airlie:
"This is the main drm pull request for v4.15.
Core:
- Atomic object lifetime fixes
- Atomic iterator improvements
- Sparse/smatch fixes
- Legacy kms ioctls to be interruptible
- EDID override improvements
- fb/gem helper cleanups
- Simple outreachy patches
- Documentation improvements
- Fix dma-buf rcu races
- DRM mode object leasing for improving VR use cases.
- vgaarb improvements for non-x86 platforms.
New driver:
- tve200: Faraday Technology TVE200 block.
This "TV Encoder" encodes a ITU-T BT.656 stream and can be found in
the StorLink SL3516 (later Cortina Systems CS3516) as well as the
Grain Media GM8180.
New bridges:
- SiI9234 support
New panels:
- S6E63J0X03, OTM8009A, Seiko 43WVF1G, 7" rpi touch panel, Toshiba
LT089AC19000, Innolux AT043TN24
i915:
- Remove Coffeelake from alpha support
- Cannonlake workarounds
- Infoframe refactoring for DisplayPort
- VBT updates
- DisplayPort vswing/emph/buffer translation refactoring
- CCS fixes
- Restore GPU clock boost on missed vblanks
- Scatter list updates for userptr allocations
- Gen9+ transition watermarks
- Display IPC (Isochronous Priority Control)
- Private PAT management
- GVT: improved error handling and pci config sanitizing
- Execlist refactoring
- Transparent Huge Page support
- User defined priorities support
- HuC/GuC firmware refactoring
- DP MST fixes
- eDP power sequencing fixes
- Use RCU instead of stop_machine
- PSR state tracking support
- Eviction fixes
- BDW DP aux channel timeout fixes
- LSPCON fixes
- Cannonlake PLL fixes
amdgpu:
- Per VM BO support
- Powerplay cleanups
- CI powerplay support
- PASID mgr for kfd
- SR-IOV fixes
- initial GPU reset for vega10
- Prime mmap support
- TTM updates
- Clock query interface for Raven
- Fence to handle ioctl
- UVD encode ring support on Polaris
- Transparent huge page DMA support
- Compute LRU pipe tweaks
- BO flag to allow buffers to opt out of implicit sync
- CTX priority setting API
- VRAM lost infrastructure plumbing
qxl:
- fix flicker since atomic rework
amdkfd:
- Further improvements from internal AMD tree
- Usermode events
- Drop radeon support
nouveau:
- Pascal temperature sensor support
- Improved BAR2 handling
- MMU rework to support Pascal MMU
exynos:
- Improved HDMI/mixer support
- HDMI audio interface support
tegra:
- Prep work for tegra186
- Cleanup/fixes
msm:
- Preemption support for a5xx
- Display fixes for 8x96 (snapdragon 820)
- Async cursor plane fixes
- FW loading rework
- GPU debugging improvements
vc4:
- Prep for DSI panels
- fix T-format tiling scanout
- New madvise ioctl
Rockchip:
- LVDS support
omapdrm:
- omap4 HDMI CEC support
etnaviv:
- GPU performance counters groundwork
sun4i:
- refactor driver load + TCON backend
- HDMI improvements
- A31 support
- Misc fixes
udl:
- Probe/EDID read fixes.
tilcdc:
- Misc fixes.
pl111:
- Support more variants
adv7511:
- Improve EDID handling.
- HDMI CEC support
sii8620:
- Add remote control support"
* tag 'drm-for-v4.15' of git://people.freedesktop.org/~airlied/linux: (1480 commits)
drm/rockchip: analogix_dp: Use mutex rather than spinlock
drm/mode_object: fix documentation for object lookups.
drm/i915: Reorder context-close to avoid calling i915_vma_close() under RCU
drm/i915: Move init_clock_gating() back to where it was
drm/i915: Prune the reservation shared fence array
drm/i915: Idle the GPU before shinking everything
drm/i915: Lock llist_del_first() vs llist_del_all()
drm/i915: Calculate ironlake intermediate watermarks correctly, v2.
drm/i915: Disable lazy PPGTT page table optimization for vGPU
drm/i915/execlists: Remove the priority "optimisation"
drm/i915: Filter out spurious execlists context-switch interrupts
drm/amdgpu: use irq-safe lock for kiq->ring_lock
drm/amdgpu: bypass lru touch for KIQ ring submission
drm/amdgpu: Potential uninitialized variable in amdgpu_vm_update_directories()
drm/amdgpu: potential uninitialized variable in amdgpu_vce_ring_parse_cs()
drm/amd/powerplay: initialize a variable before using it
drm/amd/powerplay: suppress KASAN out of bounds warning in vega10_populate_all_memory_levels
drm/amd/amdgpu: fix evicted VRAM bo adjudgement condition
drm/vblank: Tune drm_crtc_accurate_vblank_count() WARN down to a debug
drm/rockchip: add CONFIG_OF dependency for lvds
...
189 lines
12 KiB
C
189 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __NVIF_CLASS_H__
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#define __NVIF_CLASS_H__
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/* these class numbers are made up by us, and not nvidia-assigned */
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#define NVIF_CLASS_CLIENT /* if0000.h */ -0x00000000
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#define NVIF_CLASS_CONTROL /* if0001.h */ -0x00000001
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#define NVIF_CLASS_PERFMON /* if0002.h */ -0x00000002
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#define NVIF_CLASS_PERFDOM /* if0003.h */ -0x00000003
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#define NVIF_CLASS_SW_NV04 /* if0004.h */ -0x00000004
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#define NVIF_CLASS_SW_NV10 /* if0005.h */ -0x00000005
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#define NVIF_CLASS_SW_NV50 /* if0005.h */ -0x00000006
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#define NVIF_CLASS_SW_GF100 /* if0005.h */ -0x00000007
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#define NVIF_CLASS_MMU /* if0008.h */ 0x80000008
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#define NVIF_CLASS_MMU_NV04 /* if0008.h */ 0x80000009
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#define NVIF_CLASS_MMU_NV50 /* if0008.h */ 0x80005009
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#define NVIF_CLASS_MMU_GF100 /* if0008.h */ 0x80009009
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#define NVIF_CLASS_MEM /* if000a.h */ 0x8000000a
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#define NVIF_CLASS_MEM_NV04 /* if000b.h */ 0x8000000b
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#define NVIF_CLASS_MEM_NV50 /* if500b.h */ 0x8000500b
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#define NVIF_CLASS_MEM_GF100 /* if900b.h */ 0x8000900b
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#define NVIF_CLASS_VMM /* if000c.h */ 0x8000000c
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#define NVIF_CLASS_VMM_NV04 /* if000d.h */ 0x8000000d
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#define NVIF_CLASS_VMM_NV50 /* if500d.h */ 0x8000500d
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#define NVIF_CLASS_VMM_GF100 /* if900d.h */ 0x8000900d
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#define NVIF_CLASS_VMM_GM200 /* ifb00d.h */ 0x8000b00d
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#define NVIF_CLASS_VMM_GP100 /* ifc00d.h */ 0x8000c00d
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/* the below match nvidia-assigned (either in hw, or sw) class numbers */
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#define NV_NULL_CLASS 0x00000030
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#define NV_DEVICE /* cl0080.h */ 0x00000080
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#define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002
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#define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003
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#define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d
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#define NV50_TWOD 0x0000502d
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#define FERMI_TWOD_A 0x0000902d
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#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
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#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
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#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
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#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
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#define NV04_DISP /* cl0046.h */ 0x00000046
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#define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b
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#define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e
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#define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e
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#define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e
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#define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e
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#define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e
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#define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f
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#define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f
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#define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f
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#define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f
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#define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f
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#define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f
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#define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f
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#define NV50_DISP /* cl5070.h */ 0x00005070
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#define G82_DISP /* cl5070.h */ 0x00008270
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#define GT200_DISP /* cl5070.h */ 0x00008370
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#define GT214_DISP /* cl5070.h */ 0x00008570
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#define GT206_DISP /* cl5070.h */ 0x00008870
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#define GF110_DISP /* cl5070.h */ 0x00009070
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#define GK104_DISP /* cl5070.h */ 0x00009170
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#define GK110_DISP /* cl5070.h */ 0x00009270
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#define GM107_DISP /* cl5070.h */ 0x00009470
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#define GM200_DISP /* cl5070.h */ 0x00009570
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#define GP100_DISP /* cl5070.h */ 0x00009770
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#define GP102_DISP /* cl5070.h */ 0x00009870
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#define NV31_MPEG 0x00003174
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#define G82_MPEG 0x00008274
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#define NV74_VP2 0x00007476
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#define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a
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#define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a
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#define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a
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#define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a
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#define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a
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#define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b
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#define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b
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#define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b
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#define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b
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#define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b
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#define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c
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#define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c
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#define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c
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#define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c
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#define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c
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#define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c
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#define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c
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#define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d
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#define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d
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#define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d
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#define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d
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#define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d
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#define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d
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#define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d
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#define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d
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#define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d
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#define GM200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d
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#define GP100_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000977d
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#define GP102_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000987d
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#define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e
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#define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e
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#define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e
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#define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e
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#define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e
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#define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e
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#define NV50_TESLA 0x00005097
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#define G82_TESLA 0x00008297
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#define GT200_TESLA 0x00008397
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#define GT214_TESLA 0x00008597
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#define GT21A_TESLA 0x00008697
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#define FERMI_A /* cl9097.h */ 0x00009097
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#define FERMI_B /* cl9097.h */ 0x00009197
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#define FERMI_C /* cl9097.h */ 0x00009297
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#define KEPLER_A /* cl9097.h */ 0x0000a097
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#define KEPLER_B /* cl9097.h */ 0x0000a197
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#define KEPLER_C /* cl9097.h */ 0x0000a297
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#define MAXWELL_A /* cl9097.h */ 0x0000b097
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#define MAXWELL_B /* cl9097.h */ 0x0000b197
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#define PASCAL_A /* cl9097.h */ 0x0000c097
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#define PASCAL_B /* cl9097.h */ 0x0000c197
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#define NV74_BSP 0x000074b0
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#define GT212_MSVLD 0x000085b1
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#define IGT21A_MSVLD 0x000086b1
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#define G98_MSVLD 0x000088b1
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#define GF100_MSVLD 0x000090b1
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#define GK104_MSVLD 0x000095b1
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#define GT212_MSPDEC 0x000085b2
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#define G98_MSPDEC 0x000088b2
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#define GF100_MSPDEC 0x000090b2
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#define GK104_MSPDEC 0x000095b2
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#define GT212_MSPPP 0x000085b3
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#define G98_MSPPP 0x000088b3
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#define GF100_MSPPP 0x000090b3
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#define G98_SEC 0x000088b4
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#define GT212_DMA 0x000085b5
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#define FERMI_DMA 0x000090b5
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#define KEPLER_DMA_COPY_A 0x0000a0b5
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#define MAXWELL_DMA_COPY_A 0x0000b0b5
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#define PASCAL_DMA_COPY_A 0x0000c0b5
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#define PASCAL_DMA_COPY_B 0x0000c1b5
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#define FERMI_DECOMPRESS 0x000090b8
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#define NV50_COMPUTE 0x000050c0
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#define GT214_COMPUTE 0x000085c0
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#define FERMI_COMPUTE_A 0x000090c0
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#define FERMI_COMPUTE_B 0x000091c0
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#define KEPLER_COMPUTE_A 0x0000a0c0
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#define KEPLER_COMPUTE_B 0x0000a1c0
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#define MAXWELL_COMPUTE_A 0x0000b0c0
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#define MAXWELL_COMPUTE_B 0x0000b1c0
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#define PASCAL_COMPUTE_A 0x0000c0c0
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#define PASCAL_COMPUTE_B 0x0000c1c0
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#define NV74_CIPHER 0x000074c1
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#endif
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