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e20043b476
Move the asm/xor.h headers to lib/raid/xor/$(SRCARCH)/xor_arch.h and include/linux/raid/xor_impl.h to lib/raid/xor/xor_impl.h so that the xor.ko module implementation is self-contained in lib/raid/. As this remove the asm-generic mechanism a new kconfig symbol is added to indicate that a architecture-specific implementations exists, and xor_arch.h should be included. Link: https://lkml.kernel.org/r/20260327061704.3707577-22-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Eric Biggers <ebiggers@kernel.org> Tested-by: Eric Biggers <ebiggers@kernel.org> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: Andreas Larsson <andreas@gaisler.com> Cc: Anton Ivanov <anton.ivanov@cambridgegreys.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Borislav Petkov (AMD)" <bp@alien8.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Mason <clm@fb.com> Cc: Christian Borntraeger <borntraeger@linux.ibm.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: David S. Miller <davem@davemloft.net> Cc: David Sterba <dsterba@suse.com> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jason A. Donenfeld <jason@zx2c4.com> Cc: Johannes Berg <johannes@sipsolutions.net> Cc: Li Nan <linan122@huawei.com> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> Cc: Magnus Lindholm <linmag7@gmail.com> Cc: Matt Turner <mattst88@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Richard Weinberger <richard@nod.at> Cc: Russell King <linux@armlinux.org.uk> Cc: Song Liu <song@kernel.org> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Ted Ts'o <tytso@mit.edu> Cc: Vasily Gorbik <gor@linux.ibm.com> Cc: WANG Xuerui <kernel@xen0n.name> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
532 lines
13 KiB
C
532 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Optimized XOR parity functions for MMX.
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*
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* Copyright (C) 1998 Ingo Molnar.
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*/
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#include <asm/fpu/api.h>
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#include "xor_impl.h"
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#include "xor_arch.h"
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#define LD(x, y) " movq 8*("#x")(%1), %%mm"#y" ;\n"
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#define ST(x, y) " movq %%mm"#y", 8*("#x")(%1) ;\n"
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#define XO1(x, y) " pxor 8*("#x")(%2), %%mm"#y" ;\n"
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#define XO2(x, y) " pxor 8*("#x")(%3), %%mm"#y" ;\n"
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#define XO3(x, y) " pxor 8*("#x")(%4), %%mm"#y" ;\n"
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#define XO4(x, y) " pxor 8*("#x")(%5), %%mm"#y" ;\n"
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static void
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xor_pII_mmx_2(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2)
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{
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unsigned long lines = bytes >> 7;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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LD(i, 0) \
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LD(i + 1, 1) \
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LD(i + 2, 2) \
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LD(i + 3, 3) \
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XO1(i, 0) \
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ST(i, 0) \
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XO1(i+1, 1) \
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ST(i+1, 1) \
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XO1(i + 2, 2) \
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ST(i + 2, 2) \
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XO1(i + 3, 3) \
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ST(i + 3, 3)
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" addl $128, %1 ;\n"
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" addl $128, %2 ;\n"
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" decl %0 ;\n"
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" jnz 1b ;\n"
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: "+r" (lines),
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"+r" (p1), "+r" (p2)
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:
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_pII_mmx_3(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2,
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const unsigned long * __restrict p3)
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{
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unsigned long lines = bytes >> 7;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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LD(i, 0) \
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LD(i + 1, 1) \
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LD(i + 2, 2) \
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LD(i + 3, 3) \
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XO1(i, 0) \
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XO1(i + 1, 1) \
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XO1(i + 2, 2) \
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XO1(i + 3, 3) \
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XO2(i, 0) \
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ST(i, 0) \
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XO2(i + 1, 1) \
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ST(i + 1, 1) \
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XO2(i + 2, 2) \
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ST(i + 2, 2) \
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XO2(i + 3, 3) \
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ST(i + 3, 3)
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" addl $128, %1 ;\n"
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" addl $128, %2 ;\n"
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" addl $128, %3 ;\n"
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" decl %0 ;\n"
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" jnz 1b ;\n"
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: "+r" (lines),
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"+r" (p1), "+r" (p2), "+r" (p3)
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:
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_pII_mmx_4(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2,
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const unsigned long * __restrict p3,
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const unsigned long * __restrict p4)
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{
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unsigned long lines = bytes >> 7;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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LD(i, 0) \
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LD(i + 1, 1) \
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LD(i + 2, 2) \
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LD(i + 3, 3) \
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XO1(i, 0) \
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XO1(i + 1, 1) \
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XO1(i + 2, 2) \
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XO1(i + 3, 3) \
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XO2(i, 0) \
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XO2(i + 1, 1) \
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XO2(i + 2, 2) \
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XO2(i + 3, 3) \
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XO3(i, 0) \
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ST(i, 0) \
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XO3(i + 1, 1) \
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ST(i + 1, 1) \
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XO3(i + 2, 2) \
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ST(i + 2, 2) \
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XO3(i + 3, 3) \
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ST(i + 3, 3)
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" addl $128, %1 ;\n"
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" addl $128, %2 ;\n"
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" addl $128, %3 ;\n"
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" addl $128, %4 ;\n"
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" decl %0 ;\n"
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" jnz 1b ;\n"
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: "+r" (lines),
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"+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4)
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:
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_pII_mmx_5(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2,
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const unsigned long * __restrict p3,
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const unsigned long * __restrict p4,
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const unsigned long * __restrict p5)
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{
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unsigned long lines = bytes >> 7;
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kernel_fpu_begin();
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/* Make sure GCC forgets anything it knows about p4 or p5,
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such that it won't pass to the asm volatile below a
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register that is shared with any other variable. That's
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because we modify p4 and p5 there, but we can't mark them
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as read/write, otherwise we'd overflow the 10-asm-operands
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limit of GCC < 3.1. */
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asm("" : "+r" (p4), "+r" (p5));
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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LD(i, 0) \
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LD(i + 1, 1) \
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LD(i + 2, 2) \
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LD(i + 3, 3) \
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XO1(i, 0) \
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XO1(i + 1, 1) \
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XO1(i + 2, 2) \
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XO1(i + 3, 3) \
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XO2(i, 0) \
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XO2(i + 1, 1) \
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XO2(i + 2, 2) \
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XO2(i + 3, 3) \
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XO3(i, 0) \
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XO3(i + 1, 1) \
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XO3(i + 2, 2) \
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XO3(i + 3, 3) \
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XO4(i, 0) \
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ST(i, 0) \
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XO4(i + 1, 1) \
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ST(i + 1, 1) \
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XO4(i + 2, 2) \
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ST(i + 2, 2) \
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XO4(i + 3, 3) \
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ST(i + 3, 3)
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" addl $128, %1 ;\n"
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" addl $128, %2 ;\n"
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" addl $128, %3 ;\n"
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" addl $128, %4 ;\n"
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" addl $128, %5 ;\n"
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" decl %0 ;\n"
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" jnz 1b ;\n"
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: "+r" (lines),
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"+r" (p1), "+r" (p2), "+r" (p3)
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: "r" (p4), "r" (p5)
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: "memory");
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/* p4 and p5 were modified, and now the variables are dead.
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Clobber them just to be sure nobody does something stupid
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like assuming they have some legal value. */
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asm("" : "=r" (p4), "=r" (p5));
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kernel_fpu_end();
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}
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#undef LD
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#undef XO1
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#undef XO2
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#undef XO3
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#undef XO4
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#undef ST
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#undef BLOCK
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static void
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xor_p5_mmx_2(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2)
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{
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unsigned long lines = bytes >> 6;
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kernel_fpu_begin();
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asm volatile(
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" .align 32 ;\n"
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" 1: ;\n"
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" movq (%1), %%mm0 ;\n"
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" movq 8(%1), %%mm1 ;\n"
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" pxor (%2), %%mm0 ;\n"
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" movq 16(%1), %%mm2 ;\n"
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" movq %%mm0, (%1) ;\n"
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" pxor 8(%2), %%mm1 ;\n"
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" movq 24(%1), %%mm3 ;\n"
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" movq %%mm1, 8(%1) ;\n"
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" pxor 16(%2), %%mm2 ;\n"
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" movq 32(%1), %%mm4 ;\n"
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" movq %%mm2, 16(%1) ;\n"
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" pxor 24(%2), %%mm3 ;\n"
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" movq 40(%1), %%mm5 ;\n"
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" movq %%mm3, 24(%1) ;\n"
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" pxor 32(%2), %%mm4 ;\n"
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" movq 48(%1), %%mm6 ;\n"
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" movq %%mm4, 32(%1) ;\n"
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" pxor 40(%2), %%mm5 ;\n"
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" movq 56(%1), %%mm7 ;\n"
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" movq %%mm5, 40(%1) ;\n"
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" pxor 48(%2), %%mm6 ;\n"
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" pxor 56(%2), %%mm7 ;\n"
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" movq %%mm6, 48(%1) ;\n"
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" movq %%mm7, 56(%1) ;\n"
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" addl $64, %1 ;\n"
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" addl $64, %2 ;\n"
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" decl %0 ;\n"
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" jnz 1b ;\n"
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: "+r" (lines),
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"+r" (p1), "+r" (p2)
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:
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_p5_mmx_3(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2,
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const unsigned long * __restrict p3)
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{
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unsigned long lines = bytes >> 6;
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kernel_fpu_begin();
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asm volatile(
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" .align 32,0x90 ;\n"
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" 1: ;\n"
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" movq (%1), %%mm0 ;\n"
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" movq 8(%1), %%mm1 ;\n"
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" pxor (%2), %%mm0 ;\n"
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" movq 16(%1), %%mm2 ;\n"
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" pxor 8(%2), %%mm1 ;\n"
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" pxor (%3), %%mm0 ;\n"
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" pxor 16(%2), %%mm2 ;\n"
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" movq %%mm0, (%1) ;\n"
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" pxor 8(%3), %%mm1 ;\n"
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" pxor 16(%3), %%mm2 ;\n"
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" movq 24(%1), %%mm3 ;\n"
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" movq %%mm1, 8(%1) ;\n"
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" movq 32(%1), %%mm4 ;\n"
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" movq 40(%1), %%mm5 ;\n"
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" pxor 24(%2), %%mm3 ;\n"
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" movq %%mm2, 16(%1) ;\n"
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" pxor 32(%2), %%mm4 ;\n"
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" pxor 24(%3), %%mm3 ;\n"
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" pxor 40(%2), %%mm5 ;\n"
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" movq %%mm3, 24(%1) ;\n"
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" pxor 32(%3), %%mm4 ;\n"
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" pxor 40(%3), %%mm5 ;\n"
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" movq 48(%1), %%mm6 ;\n"
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" movq %%mm4, 32(%1) ;\n"
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" movq 56(%1), %%mm7 ;\n"
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" pxor 48(%2), %%mm6 ;\n"
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" movq %%mm5, 40(%1) ;\n"
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" pxor 56(%2), %%mm7 ;\n"
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" pxor 48(%3), %%mm6 ;\n"
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" pxor 56(%3), %%mm7 ;\n"
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" movq %%mm6, 48(%1) ;\n"
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" movq %%mm7, 56(%1) ;\n"
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" addl $64, %1 ;\n"
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" addl $64, %2 ;\n"
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" addl $64, %3 ;\n"
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" decl %0 ;\n"
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" jnz 1b ;\n"
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: "+r" (lines),
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"+r" (p1), "+r" (p2), "+r" (p3)
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:
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: "memory" );
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kernel_fpu_end();
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}
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static void
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xor_p5_mmx_4(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2,
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const unsigned long * __restrict p3,
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const unsigned long * __restrict p4)
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{
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unsigned long lines = bytes >> 6;
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kernel_fpu_begin();
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asm volatile(
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" .align 32,0x90 ;\n"
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" 1: ;\n"
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" movq (%1), %%mm0 ;\n"
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" movq 8(%1), %%mm1 ;\n"
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" pxor (%2), %%mm0 ;\n"
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" movq 16(%1), %%mm2 ;\n"
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" pxor 8(%2), %%mm1 ;\n"
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" pxor (%3), %%mm0 ;\n"
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" pxor 16(%2), %%mm2 ;\n"
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" pxor 8(%3), %%mm1 ;\n"
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" pxor (%4), %%mm0 ;\n"
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" movq 24(%1), %%mm3 ;\n"
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" pxor 16(%3), %%mm2 ;\n"
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" pxor 8(%4), %%mm1 ;\n"
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" movq %%mm0, (%1) ;\n"
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" movq 32(%1), %%mm4 ;\n"
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" pxor 24(%2), %%mm3 ;\n"
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" pxor 16(%4), %%mm2 ;\n"
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" movq %%mm1, 8(%1) ;\n"
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" movq 40(%1), %%mm5 ;\n"
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" pxor 32(%2), %%mm4 ;\n"
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" pxor 24(%3), %%mm3 ;\n"
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" movq %%mm2, 16(%1) ;\n"
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" pxor 40(%2), %%mm5 ;\n"
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" pxor 32(%3), %%mm4 ;\n"
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" pxor 24(%4), %%mm3 ;\n"
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" movq %%mm3, 24(%1) ;\n"
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" movq 56(%1), %%mm7 ;\n"
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" movq 48(%1), %%mm6 ;\n"
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" pxor 40(%3), %%mm5 ;\n"
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" pxor 32(%4), %%mm4 ;\n"
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" pxor 48(%2), %%mm6 ;\n"
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" movq %%mm4, 32(%1) ;\n"
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" pxor 56(%2), %%mm7 ;\n"
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" pxor 40(%4), %%mm5 ;\n"
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" pxor 48(%3), %%mm6 ;\n"
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" pxor 56(%3), %%mm7 ;\n"
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" movq %%mm5, 40(%1) ;\n"
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" pxor 48(%4), %%mm6 ;\n"
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" pxor 56(%4), %%mm7 ;\n"
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" movq %%mm6, 48(%1) ;\n"
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" movq %%mm7, 56(%1) ;\n"
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" addl $64, %1 ;\n"
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" addl $64, %2 ;\n"
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" addl $64, %3 ;\n"
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" addl $64, %4 ;\n"
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" decl %0 ;\n"
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" jnz 1b ;\n"
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: "+r" (lines),
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"+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4)
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:
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_p5_mmx_5(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2,
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const unsigned long * __restrict p3,
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const unsigned long * __restrict p4,
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const unsigned long * __restrict p5)
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{
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unsigned long lines = bytes >> 6;
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kernel_fpu_begin();
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/* Make sure GCC forgets anything it knows about p4 or p5,
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such that it won't pass to the asm volatile below a
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register that is shared with any other variable. That's
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because we modify p4 and p5 there, but we can't mark them
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as read/write, otherwise we'd overflow the 10-asm-operands
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limit of GCC < 3.1. */
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asm("" : "+r" (p4), "+r" (p5));
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asm volatile(
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" .align 32,0x90 ;\n"
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" 1: ;\n"
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" movq (%1), %%mm0 ;\n"
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" movq 8(%1), %%mm1 ;\n"
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" pxor (%2), %%mm0 ;\n"
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" pxor 8(%2), %%mm1 ;\n"
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" movq 16(%1), %%mm2 ;\n"
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" pxor (%3), %%mm0 ;\n"
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" pxor 8(%3), %%mm1 ;\n"
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" pxor 16(%2), %%mm2 ;\n"
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" pxor (%4), %%mm0 ;\n"
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" pxor 8(%4), %%mm1 ;\n"
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" pxor 16(%3), %%mm2 ;\n"
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" movq 24(%1), %%mm3 ;\n"
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" pxor (%5), %%mm0 ;\n"
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" pxor 8(%5), %%mm1 ;\n"
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" movq %%mm0, (%1) ;\n"
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" pxor 16(%4), %%mm2 ;\n"
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" pxor 24(%2), %%mm3 ;\n"
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" movq %%mm1, 8(%1) ;\n"
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" pxor 16(%5), %%mm2 ;\n"
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" pxor 24(%3), %%mm3 ;\n"
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" movq 32(%1), %%mm4 ;\n"
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" movq %%mm2, 16(%1) ;\n"
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" pxor 24(%4), %%mm3 ;\n"
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" pxor 32(%2), %%mm4 ;\n"
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" movq 40(%1), %%mm5 ;\n"
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" pxor 24(%5), %%mm3 ;\n"
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" pxor 32(%3), %%mm4 ;\n"
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" pxor 40(%2), %%mm5 ;\n"
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" movq %%mm3, 24(%1) ;\n"
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" pxor 32(%4), %%mm4 ;\n"
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" pxor 40(%3), %%mm5 ;\n"
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" movq 48(%1), %%mm6 ;\n"
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" movq 56(%1), %%mm7 ;\n"
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" pxor 32(%5), %%mm4 ;\n"
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" pxor 40(%4), %%mm5 ;\n"
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" pxor 48(%2), %%mm6 ;\n"
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" pxor 56(%2), %%mm7 ;\n"
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" movq %%mm4, 32(%1) ;\n"
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" pxor 48(%3), %%mm6 ;\n"
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" pxor 56(%3), %%mm7 ;\n"
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" pxor 40(%5), %%mm5 ;\n"
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" pxor 48(%4), %%mm6 ;\n"
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" pxor 56(%4), %%mm7 ;\n"
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" movq %%mm5, 40(%1) ;\n"
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" pxor 48(%5), %%mm6 ;\n"
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" pxor 56(%5), %%mm7 ;\n"
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" movq %%mm6, 48(%1) ;\n"
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" movq %%mm7, 56(%1) ;\n"
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|
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" addl $64, %1 ;\n"
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" addl $64, %2 ;\n"
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" addl $64, %3 ;\n"
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" addl $64, %4 ;\n"
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" addl $64, %5 ;\n"
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" decl %0 ;\n"
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" jnz 1b ;\n"
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: "+r" (lines),
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"+r" (p1), "+r" (p2), "+r" (p3)
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: "r" (p4), "r" (p5)
|
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: "memory");
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|
|
|
/* p4 and p5 were modified, and now the variables are dead.
|
|
Clobber them just to be sure nobody does something stupid
|
|
like assuming they have some legal value. */
|
|
asm("" : "=r" (p4), "=r" (p5));
|
|
|
|
kernel_fpu_end();
|
|
}
|
|
|
|
struct xor_block_template xor_block_pII_mmx = {
|
|
.name = "pII_mmx",
|
|
.do_2 = xor_pII_mmx_2,
|
|
.do_3 = xor_pII_mmx_3,
|
|
.do_4 = xor_pII_mmx_4,
|
|
.do_5 = xor_pII_mmx_5,
|
|
};
|
|
|
|
struct xor_block_template xor_block_p5_mmx = {
|
|
.name = "p5_mmx",
|
|
.do_2 = xor_p5_mmx_2,
|
|
.do_3 = xor_p5_mmx_3,
|
|
.do_4 = xor_p5_mmx_4,
|
|
.do_5 = xor_p5_mmx_5,
|
|
};
|