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9be5c47908
On a vast majority of Qualcomm chipsets DisplayPort controller can support several MST streams (up to 4x). To support MST these chipsets use up to 4 stream pixel clocks for the DisplayPort controller and several extra register regions. Expand corresponding region and clock bindings for these platforms and fix example schema files to follow updated bindings. Note: On chipsets that support MST, the number of streams supported can vary between controllers. For example, SA8775P supports 4 MST streams on mdss_dp0 but only 2 streams on mdss_dp1. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Jessica Zhang <jessica.zhang@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/672585/ Link: https://lore.kernel.org/r/20250903-dp_mst_bindings-v8-7-7526f0311eaa@oss.qualcomm.com
444 lines
13 KiB
YAML
444 lines
13 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sar2130p-mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SAR2130P Display MDSS
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maintainers:
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- Dmitry Baryshkov <lumag@kernel.org>
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description:
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SAR2310P MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
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DPU display controller, DSI and DP interfaces etc.
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$ref: /schemas/display/msm/mdss-common.yaml#
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properties:
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compatible:
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const: qcom,sar2130p-mdss
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clocks:
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items:
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- description: Display MDSS AHB
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- description: Display AHB
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- description: Display hf AXI
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- description: Display core
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iommus:
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maxItems: 1
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interconnects:
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items:
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- description: Interconnect path from mdp0 port to the data bus
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- description: Interconnect path from CPU to the reg bus
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interconnect-names:
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items:
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- const: mdp0-mem
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- const: cpu-cfg
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,sar2130p-dpu
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"^displayport-controller@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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contains:
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const: qcom,sar2130p-dp
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"^dsi@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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contains:
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const: qcom,sar2130p-dsi-ctrl
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"^phy@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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compatible:
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const: qcom,sar2130p-dsi-phy-5nm
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required:
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- compatible
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom,rpmhpd.h>
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#include <dt-bindings/phy/phy-qcom-qmp.h>
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display-subsystem@ae00000 {
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compatible = "qcom,sar2130p-mdss";
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reg = <0x0ae00000 0x1000>;
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reg-names = "mdss";
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interconnects = <&mmss_noc_master_mdp &mc_virt_slave_ebi1>,
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<&gem_noc_master_appss_proc &config_noc_slave_display_cfg>;
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interconnect-names = "mdp0-mem", "cpu-cfg";
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resets = <&dispcc_disp_cc_mdss_core_bcr>;
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power-domains = <&dispcc_mdss_gdsc>;
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clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
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<&gcc_gcc_disp_ahb_clk>,
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<&gcc_gcc_disp_hf_axi_clk>,
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<&dispcc_disp_cc_mdss_mdp_clk>;
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clock-names = "iface", "bus", "nrt_bus", "core";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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iommus = <&apps_smmu 0x1c00 0x2>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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display-controller@ae01000 {
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compatible = "qcom,sar2130p-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc_gcc_disp_ahb_clk>,
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<&gcc_gcc_disp_hf_axi_clk>,
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<&dispcc_disp_cc_mdss_ahb_clk>,
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<&dispcc_disp_cc_mdss_mdp_lut_clk>,
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<&dispcc_disp_cc_mdss_mdp_clk>,
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<&dispcc_disp_cc_mdss_vsync_clk>;
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clock-names = "bus",
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"nrt_bus",
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"iface",
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"lut",
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"core",
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"vsync";
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assigned-clocks = <&dispcc_disp_cc_mdss_vsync_clk>;
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assigned-clock-rates = <19200000>;
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operating-points-v2 = <&mdp_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf0_out: endpoint {
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remote-endpoint = <&mdss_dp0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&mdss_dsi0_in>;
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};
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};
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port@2 {
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reg = <2>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&mdss_dsi1_in>;
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};
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};
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};
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mdp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-200000000 {
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opp-hz = /bits/ 64 <200000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-325000000 {
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opp-hz = /bits/ 64 <325000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-375000000 {
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opp-hz = /bits/ 64 <375000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-514000000 {
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opp-hz = /bits/ 64 <514000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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displayport-controller@ae90000 {
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compatible = "qcom,sar2130p-dp",
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"qcom,sm8350-dp";
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reg = <0xae90000 0x200>,
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<0xae90200 0x200>,
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<0xae90400 0xc00>,
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<0xae91000 0x400>,
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<0xae91400 0x400>;
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interrupt-parent = <&mdss>;
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interrupts = <12>;
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clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
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<&dispcc_disp_cc_mdss_dptx0_aux_clk>,
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<&dispcc_disp_cc_mdss_dptx0_link_clk>,
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<&dispcc_disp_cc_mdss_dptx0_link_intf_clk>,
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<&dispcc_disp_cc_mdss_dptx0_pixel0_clk>,
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<&dispcc_disp_cc_mdss_dptx0_pixel1_clk>;
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clock-names = "core_iface",
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"core_aux",
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"ctrl_link",
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"ctrl_link_iface",
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"stream_pixel",
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"stream_1_pixel";
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assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>,
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<&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>,
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<&dispcc_disp_cc_mdss_dptx0_pixel1_clk_src>;
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assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>,
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<&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>,
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<&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>;
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phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
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phy-names = "dp";
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#sound-dai-cells = <0>;
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operating-points-v2 = <&dp_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dp0_in: endpoint {
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remote-endpoint = <&dpu_intf0_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dp0_out: endpoint {
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remote-endpoint = <&usb_dp_qmpphy_dp_in>;
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};
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};
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};
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dp_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-162000000 {
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opp-hz = /bits/ 64 <162000000>;
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required-opps = <&rpmhpd_opp_low_svs_d1>;
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};
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opp-270000000 {
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opp-hz = /bits/ 64 <270000000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-540000000 {
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opp-hz = /bits/ 64 <540000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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opp-810000000 {
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opp-hz = /bits/ 64 <810000000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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};
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};
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dsi@ae94000 {
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compatible = "qcom,sar2130p-dsi-ctrl",
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"qcom,mdss-dsi-ctrl";
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reg = <0x0ae94000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&dispcc_disp_cc_mdss_byte0_clk>,
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<&dispcc_disp_cc_mdss_byte0_intf_clk>,
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<&dispcc_disp_cc_mdss_pclk0_clk>,
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<&dispcc_disp_cc_mdss_esc0_clk>,
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<&dispcc_disp_cc_mdss_ahb_clk>,
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<&gcc_gcc_disp_hf_axi_clk>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc_disp_cc_mdss_byte0_clk_src>,
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<&dispcc_disp_cc_mdss_pclk0_clk_src>;
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assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&mdss_dsi0_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi0_out: endpoint {
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};
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};
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};
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dsi_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-187500000 {
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opp-hz = /bits/ 64 <187500000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-300000000 {
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opp-hz = /bits/ 64 <300000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-358000000 {
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opp-hz = /bits/ 64 <358000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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};
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mdss_dsi0_phy: phy@ae94400 {
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compatible = "qcom,sar2130p-dsi-phy-5nm";
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reg = <0x0ae95000 0x200>,
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<0x0ae95200 0x280>,
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<0x0ae95500 0x400>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
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<&rpmhcc_rpmh_cxo_clk>;
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clock-names = "iface", "ref";
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};
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dsi@ae96000 {
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compatible = "qcom,sar2130p-dsi-ctrl",
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"qcom,mdss-dsi-ctrl";
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reg = <0x0ae96000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <5>;
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clocks = <&dispcc_disp_cc_mdss_byte1_clk>,
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<&dispcc_disp_cc_mdss_byte1_intf_clk>,
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<&dispcc_disp_cc_mdss_pclk1_clk>,
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<&dispcc_disp_cc_mdss_esc1_clk>,
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<&dispcc_disp_cc_mdss_ahb_clk>,
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<&gcc_gcc_disp_hf_axi_clk>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc_disp_cc_mdss_byte1_clk_src>,
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<&dispcc_disp_cc_mdss_pclk1_clk_src>;
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assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmhpd RPMHPD_MMCX>;
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phys = <&mdss_dsi1_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdss_dsi1_in: endpoint {
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remote-endpoint = <&dpu_intf2_out>;
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};
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};
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port@1 {
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reg = <1>;
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mdss_dsi1_out: endpoint {
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};
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};
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};
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};
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mdss_dsi1_phy: phy@ae97000 {
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compatible = "qcom,sar2130p-dsi-phy-5nm";
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reg = <0x0ae97000 0x200>,
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<0x0ae97200 0x280>,
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<0x0ae97500 0x400>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc_disp_cc_mdss_ahb_clk>,
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<&rpmhcc_rpmh_cxo_clk>;
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clock-names = "iface", "ref";
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};
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};
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...
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