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Generally at most 1 blank line is the standard style for DT schema files. Remove the few cases with more than 1 so that the yamllint check for this can be enabled. Acked-by: Lee Jones <lee@kernel.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> # remoteproc Acked-by: Georgi Djakov <djakov@kernel.org> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Andi Shyti <andi.shyti@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Uwe Kleine-König <ukleinek@kernel.org> # for allwinner,sun4i-a10-pwm.yaml Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> # mtd Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> # For PCI controller bindings Link: https://patch.msgid.link/20251023143957.2899600-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
91 lines
2.8 KiB
YAML
91 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2-peripheral-props.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Peripheral Properties for Qualcomm External Bus Interface 2 (EBI2)
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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properties:
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# SLOW chip selects
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qcom,xmem-recovery-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The time the memory continues to drive the data bus after OE
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is de-asserted, in order to avoid contention on the data bus.
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They are inserted when reading one CS and switching to another
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CS or read followed by write on the same CS. Minimum value is
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actually 1, so a value of 0 will still yield 1 recovery cycle.
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minimum: 0
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maximum: 15
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qcom,xmem-write-hold-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The extra cycles inserted after every write minimum 1. The
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data out is driven from the time WE is asserted until CS is
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asserted. With a hold of 1 (value = 0), the CS stays active
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for 1 extra cycle, etc.
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minimum: 0
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maximum: 15
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qcom,xmem-write-delta-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The initial latency for write cycles inserted for the first
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write to a page or burst memory.
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minimum: 0
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maximum: 255
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qcom,xmem-read-delta-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The initial latency for read cycles inserted for the first
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read to a page or burst memory.
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minimum: 0
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maximum: 255
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qcom,xmem-write-wait-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The number of wait cycles for every write access.
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minimum: 0
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maximum: 15
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qcom,xmem-read-wait-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The number of wait cycles for every read access.
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minimum: 0
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maximum: 15
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# FAST chip selects
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qcom,xmem-address-hold-enable:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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Holds the address for an extra cycle to meet hold time
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requirements with ADV assertion, when set to 1.
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enum: [ 0, 1 ]
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qcom,xmem-adv-to-oe-recovery-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The number of cycles elapsed before an OE assertion, with
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respect to the cycle where ADV (address valid) is asserted.
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minimum: 0
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maximum: 3
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qcom,xmem-read-hold-cycles:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The length in cycles of the first segment of a read transfer.
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For a single read transfer this will be the time from CS
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assertion to OE assertion.
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minimum: 0
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maximum: 15
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additionalProperties: true
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