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8d978222e8
Add device tree bindings for AMD Versal NET EDAC for DDR controller. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20250908115649.22903-1-shubhrajyoti.datta@amd.com
42 lines
1.2 KiB
YAML
42 lines
1.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-net-ddrmc5.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Versal NET Memory Controller
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maintainers:
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- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
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description:
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The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5
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compact and extended memory interfaces. Versal NET DDR memory controller
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has an optional ECC support which correct single bit ECC errors and detect
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double bit ECC errors. It also has support for reporting other errors like
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MMCM (Mixed-Mode Clock Manager) errors and General software errors.
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properties:
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compatible:
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const: xlnx,versal-net-ddrmc5
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amd,rproc:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle to the remoteproc_r5 rproc node using which APU interacts
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with remote processor. APU primarily communicates with the RPU for
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accessing the DDRMC address space and getting error notification.
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required:
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- compatible
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- amd,rproc
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additionalProperties: false
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examples:
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- |
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memory-controller {
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compatible = "xlnx,versal-net-ddrmc5";
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amd,rproc = <&remoteproc_r5>;
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};
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