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8753827592
The Cadence HP NAND Flash Controller on supports DMA transactions through a coherent interconnect. In previous generations SoC (Stratix10 and Agilex) the interconnect was non-coherent, hence there is no need for dma-coherent property to be presence. In Agilex 5, the architecture has changed. It introduced a coherent interconnect that supports cache-coherent DMA. Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
87 lines
1.7 KiB
YAML
87 lines
1.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence NAND controller
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maintainers:
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- Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
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allOf:
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- $ref: nand-controller.yaml
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properties:
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compatible:
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items:
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- const: cdns,hp-nfc
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reg:
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items:
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- description: Controller register set
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- description: Slave DMA data port register set
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reg-names:
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items:
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- const: reg
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- const: sdma
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: nf_clk
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dmas:
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maxItems: 1
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dma-coherent: true
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iommus:
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maxItems: 1
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cdns,board-delay-ps:
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description: |
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Estimated Board delay. The value includes the total round trip
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delay for the signals and is used for deciding on values associated
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with data read capture. The example formula for SDR mode is the
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following.
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board delay = RE#PAD delay + PCB trace to device + PCB trace from device
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+ DQ PAD delay
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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nand-controller@10b80000 {
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compatible = "cdns,hp-nfc";
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reg = <0x10b80000 0x10000>,
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<0x10840000 0x10000>;
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reg-names = "reg", "sdma";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk>;
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clock-names = "nf_clk";
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cdns,board-delay-ps = <4830>;
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nand@0 {
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reg = <0>;
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};
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};
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