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SPMI PMIC Arbiter version 8 builds upon version 7 with support for up to four SPMI buses. To achieve this, the register map was slightly rearranged. Add a new binding file and compatible string for version 8 using the name 'glymur' as the Qualcomm Technologies, Inc. Glymur SoC is the first one to use PMIC arbiter version 8. This specifies the new register ranges needed only for version 8. Also document SPMI PMIC Arbiter for Qualcomm Kaanapali SoC, by adding fallback to Glymur compatible string, as it too has version 8 functionality. Signed-off-by: David Collins <david.collins@oss.qualcomm.com> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Jishnu Prakash <jishnu.prakash@oss.qualcomm.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://patch.msgid.link/20260123182039.224314-9-sboyd@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
151 lines
4.0 KiB
YAML
151 lines
4.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spmi/qcom,glymur-spmi-pmic-arb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. Glymur SPMI Controller (PMIC Arbiter v8)
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maintainers:
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- David Collins <david.collins@oss.qualcomm.com>
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description: |
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The Glymur SPMI PMIC Arbiter implements HW version 8 and it's an SPMI
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controller with wrapping arbitration logic to allow for multiple on-chip
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devices to control up to 4 SPMI separate buses.
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The PMIC Arbiter can also act as an interrupt controller, providing interrupts
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to slave devices.
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allOf:
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- $ref: /schemas/spmi/qcom,spmi-pmic-arb-common.yaml
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,kaanapali-spmi-pmic-arb
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- const: qcom,glymur-spmi-pmic-arb
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- enum:
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- qcom,glymur-spmi-pmic-arb
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reg:
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items:
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- description: core registers
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- description: tx-channel per virtual slave registers
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- description: rx-channel (called observer) per virtual slave registers
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- description: channel to PMIC peripheral mapping registers
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reg-names:
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items:
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- const: core
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- const: chnls
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- const: obsrvr
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- const: chnl_map
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ranges: true
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'#address-cells':
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const: 2
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'#size-cells':
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const: 2
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patternProperties:
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"^spmi@[a-f0-9]+$":
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type: object
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$ref: /schemas/spmi/spmi.yaml
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unevaluatedProperties: false
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properties:
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reg:
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items:
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- description: configuration registers
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- description: interrupt controller registers
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- description: channel owner EE mapping registers
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reg-names:
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items:
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- const: cnfg
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- const: intr
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- const: chnl_owner
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interrupts:
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maxItems: 1
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interrupt-names:
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const: periph_irq
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interrupt-controller: true
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'#interrupt-cells':
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const: 4
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description: |
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cell 1: slave ID for the requested interrupt (0-15)
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cell 2: peripheral ID for requested interrupt (0-255)
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cell 3: the requested peripheral interrupt (0-7)
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cell 4: interrupt flags indicating level-sense information,
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as defined in dt-bindings/interrupt-controller/irq.h
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required:
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- compatible
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- reg-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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arbiter@c400000 {
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compatible = "qcom,glymur-spmi-pmic-arb";
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reg = <0x0 0xc400000 0x0 0x3000>,
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<0x0 0xc900000 0x0 0x400000>,
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<0x0 0xc4c0000 0x0 0x400000>,
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<0x0 0xc403000 0x0 0x8000>;
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reg-names = "core", "chnls", "obsrvr", "chnl_map";
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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spmi@c426000 {
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reg = <0x0 0xc426000 0x0 0x4000>,
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<0x0 0xc8c0000 0x0 0x10000>,
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<0x0 0xc42a000 0x0 0x8000>;
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reg-names = "cnfg", "intr", "chnl_owner";
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interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "periph_irq";
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interrupt-controller;
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#interrupt-cells = <4>;
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#address-cells = <2>;
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#size-cells = <0>;
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};
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spmi@c437000 {
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reg = <0x0 0xc437000 0x0 0x4000>,
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<0x0 0xc8d0000 0x0 0x10000>,
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<0x0 0xc43b000 0x0 0x8000>;
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reg-names = "cnfg", "intr", "chnl_owner";
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interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "periph_irq";
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interrupt-controller;
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#interrupt-cells = <4>;
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#address-cells = <2>;
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#size-cells = <0>;
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};
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};
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};
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