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The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs include a Temperature Sensor Unit (TSU). The device provides real-time temperature measurements for thermal management, utilizing a single dedicated channel for temperature sensing. Compared to the previously supported RZ/G3E, the RZ/T2H and RZ/N2H SoCs do not have a reset for the TSU peripheral, and the OTP data is exposed via ARM SMC, as opposed to a system register. Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Link: https://patch.msgid.link/20260108195223.193531-5-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
118 lines
2.9 KiB
YAML
118 lines
2.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/thermal/renesas,r9a09g047-tsu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G3E Temperature Sensor Unit (TSU)
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maintainers:
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- John Madieu <john.madieu.xa@bp.renesas.com>
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description:
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The Temperature Sensor Unit (TSU) is an integrated thermal sensor that
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monitors the chip temperature on the Renesas RZ/G3E SoC. The TSU provides
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real-time temperature measurements for thermal management.
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properties:
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compatible:
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oneOf:
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- enum:
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- renesas,r9a09g047-tsu # RZ/G3E
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- renesas,r9a09g077-tsu # RZ/T2H
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- items:
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- enum:
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- renesas,r9a09g056-tsu # RZ/V2N
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- renesas,r9a09g057-tsu # RZ/V2H
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- const: renesas,r9a09g047-tsu # RZ/G3E
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- items:
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- const: renesas,r9a09g087-tsu # RZ/N2H
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- const: renesas,r9a09g077-tsu # RZ/T2H
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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power-domains:
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maxItems: 1
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interrupts:
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items:
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- description: Conversion complete interrupt signal (pulse)
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- description: Comparison result interrupt signal (level)
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interrupt-names:
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items:
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- const: adi
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- const: adcmpi
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"#thermal-sensor-cells":
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const: 0
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renesas,tsu-trim:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to system controller
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- description: offset of trim registers
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description:
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Phandle and offset to the system controller containing the TSU
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calibration trim values. The offset points to the first trim register
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(OTPTSU1TRMVAL0), with the second trim register (OTPTSU1TRMVAL1) located
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at offset + 4.
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required:
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- compatible
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- reg
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- clocks
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- power-domains
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- interrupts
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- interrupt-names
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- "#thermal-sensor-cells"
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a09g047-tsu
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then:
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required:
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- resets
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- renesas,tsu-trim
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a09g077-tsu
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then:
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properties:
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resets: false
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renesas,tsu-trim: false
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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thermal-sensor@14002000 {
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compatible = "renesas,r9a09g047-tsu";
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reg = <0x14002000 0x1000>;
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clocks = <&cpg CPG_MOD 0x10a>;
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resets = <&cpg 0xf8>;
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power-domains = <&cpg>;
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interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "adi", "adcmpi";
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#thermal-sensor-cells = <0>;
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renesas,tsu-trim = <&sys 0x330>;
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};
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