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e356289680
There was a recent update in the BSpec adding an extra step to the PLL
enable sequence, which is for programming the msgbus timer. Since we
also touch PHY registers during hw readout, let's do the programming
when starting a transaction rather than only when doing the PLL enable
sequence.
This might be the missing step that was causing the timeouts
that we have recently seen during C20 SRAM register programming
sequences. With this in place, we shouldn't need the logic to bump the
timer thresholds, since now we have a documented value that should be
set peform programming the registers. As such, let's also remove
intel_cx0_bus_check_and_bump_timer(), but keep the part that checks if
hardware really detected a timeout, which might be useful debugging
information.
v2:
- Use debug level instead of warning for the message notifying that
the hardware did not detect the timeout. (Mika)
- Got a new BSpec update clarifying that we need to program the msgbus
timer of both PHY lanes. Update the changes to reflect that.
(Gustavo)
BSpec: 64568
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230912155923.39494-1-gustavo.sousa@intel.com
288 lines
13 KiB
C
288 lines
13 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef __INTEL_CX0_PHY_REGS_H__
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#define __INTEL_CX0_PHY_REGS_H__
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#include "i915_reg_defs.h"
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#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
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#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
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#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
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#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
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#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
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_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
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_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
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_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
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_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
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#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
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#define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
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#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
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#define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
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#define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
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#define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16)
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#define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val)
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#define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
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#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
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#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
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#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
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_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
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_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
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_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
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_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
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#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
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#define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
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#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
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#define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5
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#define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16)
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#define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val)
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#define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15)
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#define XELPDP_MSGBUS_TIMEOUT_SLOW 1
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#define XELPDP_MSGBUS_TIMEOUT_FAST_US 2
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#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
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#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
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#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
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#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
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#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US 100
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#define XELPDP_PORT_RESET_END_TIMEOUT 15
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#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
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#define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
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#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
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#define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
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#define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
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#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
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_XELPDP_PORT_BUF_CTL1_LN0_A, \
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_XELPDP_PORT_BUF_CTL1_LN0_B, \
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_XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
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_XELPDP_PORT_BUF_CTL1_LN0_USBC2))
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#define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29)
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#define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28)
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#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
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#define XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK REG_GENMASK(19, 18)
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#define XELPDP_PORT_BUF_PORT_DATA_10BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 0)
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#define XELPDP_PORT_BUF_PORT_DATA_20BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1)
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#define XELPDP_PORT_BUF_PORT_DATA_40BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2)
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#define XELPDP_PORT_REVERSAL REG_BIT(16)
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#define XELPDP_PORT_BUF_IO_SELECT_TBT REG_BIT(11)
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#define XELPDP_PORT_BUF_PHY_IDLE REG_BIT(7)
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#define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6)
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#define XELPDP_TCSS_POWER_REQUEST REG_BIT(5)
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#define XELPDP_TCSS_POWER_STATE REG_BIT(4)
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#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
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#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
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#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
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_XELPDP_PORT_BUF_CTL1_LN0_A, \
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_XELPDP_PORT_BUF_CTL1_LN0_B, \
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_XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
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_XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
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#define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30))
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#define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28))
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#define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24))
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#define _XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20)
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#define _XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val)
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#define _XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16)
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#define _XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val)
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#define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \
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_XELPDP_LANE0_POWERDOWN_NEW_STATE(val), \
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_XELPDP_LANE1_POWERDOWN_NEW_STATE(val))
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#define XELPDP_LANE_POWERDOWN_NEW_STATE_MASK REG_GENMASK(3, 0)
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#define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
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#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
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#define XELPDP_PORT_BUF_CTL3(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
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_XELPDP_PORT_BUF_CTL1_LN0_A, \
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_XELPDP_PORT_BUF_CTL1_LN0_B, \
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_XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
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_XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8)
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#define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
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#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
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#define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
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#define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val)
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#define CX0_P0_STATE_ACTIVE 0x0
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#define CX0_P2_STATE_READY 0x2
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#define CX0_P2PG_STATE_DISABLE 0x9
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#define CX0_P4PG_STATE_DISABLE 0xC
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#define CX0_P2_STATE_RESET 0x2
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#define _XELPDP_PORT_MSGBUS_TIMER_LN0_A 0x640d8
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#define _XELPDP_PORT_MSGBUS_TIMER_LN0_B 0x641d8
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#define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1 0x16f258
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#define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2 0x16f458
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#define XELPDP_PORT_MSGBUS_TIMER(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
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_XELPDP_PORT_MSGBUS_TIMER_LN0_A, \
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_XELPDP_PORT_MSGBUS_TIMER_LN0_B, \
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_XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1, \
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_XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2) + (lane) * 4)
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#define XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT REG_BIT(31)
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#define XELPDP_PORT_MSGBUS_TIMER_VAL_MASK REG_GENMASK(23, 0)
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#define XELPDP_PORT_MSGBUS_TIMER_VAL REG_FIELD_PREP(XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, 0xa000)
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#define _XELPDP_PORT_CLOCK_CTL_A 0x640E0
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#define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
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#define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
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#define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
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#define XELPDP_PORT_CLOCK_CTL(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
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_XELPDP_PORT_CLOCK_CTL_A, \
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_XELPDP_PORT_CLOCK_CTL_B, \
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_XELPDP_PORT_CLOCK_CTL_USBC1, \
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_XELPDP_PORT_CLOCK_CTL_USBC2))
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#define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4))
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#define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4))
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#define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4))
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#define XELPDP_LANE_PCLK_REFCLK_ACK(lane) REG_BIT(28 - ((lane) * 4))
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#define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19)
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#define XELPDP_TBT_CLOCK_ACK REG_BIT(18)
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#define XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12)
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#define XELPDP_DDI_CLOCK_SELECT(val) REG_FIELD_PREP(XELPDP_DDI_CLOCK_SELECT_MASK, val)
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#define XELPDP_DDI_CLOCK_SELECT_NONE 0x0
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#define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8
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#define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9
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#define XELPDP_DDI_CLOCK_SELECT_TBT_162 0xc
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#define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd
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#define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe
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#define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf
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#define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10)
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#define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8)
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#define XELPDP_SSC_ENABLE_PLLA REG_BIT(1)
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#define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
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/* C10 Vendor Registers */
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#define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
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#define C10_PLL0_FRACEN REG_BIT8(4)
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#define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
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#define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
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#define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3)
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#define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
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#define C10_CMN0_REF_RANGE REG_FIELD_PREP(REG_GENMASK(4, 0), 1)
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#define C10_CMN0_REF_CLK_MPLLB_DIV REG_FIELD_PREP(REG_GENMASK(7, 5), 1)
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#define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5)
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#define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val)
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#define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
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#define C10_TX0_TX_MPLLB_SEL REG_BIT(4)
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#define C10_TX1_TERMCTL_MASK REG_GENMASK8(7, 5)
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#define C10_TX1_TERMCTL(val) REG_FIELD_PREP8(C10_TX1_TERMCTL_MASK, val)
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#define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
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#define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2)
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#define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1)
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#define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
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#define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
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#define C10_VDR_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
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#define C10_VDR_CUSTOM_WIDTH_8_10 REG_FIELD_PREP(C10_VDR_CUSTOM_WIDTH_MASK, 0)
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#define PHY_C10_VDR_OVRD 0xD71
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#define PHY_C10_VDR_OVRD_TX1 REG_BIT8(0)
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#define PHY_C10_VDR_OVRD_TX2 REG_BIT8(2)
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#define PHY_C10_VDR_PRE_OVRD_TX1 0xD80
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#define C10_PHY_OVRD_LEVEL_MASK REG_GENMASK8(5, 0)
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#define C10_PHY_OVRD_LEVEL(val) REG_FIELD_PREP8(C10_PHY_OVRD_LEVEL_MASK, val)
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#define PHY_CX0_VDROVRD_CTL(lane, tx, control) \
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(PHY_C10_VDR_PRE_OVRD_TX1 + \
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((lane) ^ (tx)) * 0x10 + (control))
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/* PIPE SPEC Defined Registers */
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#define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
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#define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6)
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/* C20 Registers */
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#define PHY_C20_WR_ADDRESS_L 0xC02
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#define PHY_C20_WR_ADDRESS_H 0xC03
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#define PHY_C20_WR_DATA_L 0xC04
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#define PHY_C20_WR_DATA_H 0xC05
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#define PHY_C20_RD_ADDRESS_L 0xC06
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#define PHY_C20_RD_ADDRESS_H 0xC07
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#define PHY_C20_RD_DATA_L 0xC08
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#define PHY_C20_RD_DATA_H 0xC09
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#define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
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#define PHY_C20_VDR_HDMI_RATE 0xD01
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#define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
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#define PHY_C20_CUSTOM_SERDES_MASK REG_GENMASK8(4, 1)
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#define PHY_C20_CUSTOM_SERDES(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_SERDES_MASK, val)
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#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
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#define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
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#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
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#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
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#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
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#define C20_PHY_TX_RATE REG_GENMASK(2, 0)
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#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
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#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
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#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
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#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
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#define C20_MPLLA_FRACEN REG_BIT(14)
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#define C20_FB_CLK_DIV4_EN REG_BIT(13)
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#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
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#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
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#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
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#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
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#define C20_MPLLB_FRACEN REG_BIT(13)
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#define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10)
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#define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
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#define C20_PHY_USE_MPLLB REG_BIT(7)
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/* C20 Phy VSwing Masks */
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#define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)
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#define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val)
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#define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
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/* C20 HDMI computed pll definitions */
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#define REFCLK_38_4_MHZ 38400000
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#define CLOCK_4999MHZ 4999999999
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#define CLOCK_9999MHZ 9999999999
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#define DATARATE_3000000000 3000000000
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#define DATARATE_3500000000 3500000000
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#define DATARATE_4000000000 4000000000
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#define MPLL_FRACN_DEN 0xFFFF
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#define SSC_UP_SPREAD REG_BIT16(9)
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#define WORD_CLK_DIV REG_BIT16(8)
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#define MPLL_TX_CLK_DIV(val) REG_FIELD_PREP16(C20_MPLLB_TX_CLK_DIV_MASK, val)
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#define MPLL_MULTIPLIER(val) REG_FIELD_PREP16(C20_MULTIPLIER_MASK, val)
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#define MPLLB_ANA_FREQ_VCO_0 0
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#define MPLLB_ANA_FREQ_VCO_1 1
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#define MPLLB_ANA_FREQ_VCO_2 2
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#define MPLLB_ANA_FREQ_VCO_3 3
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#define MPLLB_ANA_FREQ_VCO_MASK REG_GENMASK16(15, 14)
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#define MPLLB_ANA_FREQ_VCO(val) REG_FIELD_PREP16(MPLLB_ANA_FREQ_VCO_MASK, val)
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#define MPLL_DIV_MULTIPLIER_MASK REG_GENMASK16(7, 0)
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#define MPLL_DIV_MULTIPLIER(val) REG_FIELD_PREP16(MPLL_DIV_MULTIPLIER_MASK, val)
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#define CAL_DAC_CODE_31 31
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#define CAL_DAC_CODE_MASK REG_GENMASK16(14, 10)
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#define CAL_DAC_CODE(val) REG_FIELD_PREP16(CAL_DAC_CODE_MASK, val)
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#define CP_INT_GS_28 28
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#define CP_INT_GS_MASK REG_GENMASK16(6, 0)
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#define CP_INT_GS(val) REG_FIELD_PREP16(CP_INT_GS_MASK, val)
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#define CP_PROP_GS_30 30
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#define CP_PROP_GS_MASK REG_GENMASK16(13, 7)
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#define CP_PROP_GS(val) REG_FIELD_PREP16(CP_PROP_GS_MASK, val)
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#define CP_INT_6 6
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#define CP_INT_MASK REG_GENMASK16(6, 0)
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#define CP_INT(val) REG_FIELD_PREP16(CP_INT_MASK, val)
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#define CP_PROP_20 20
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#define CP_PROP_MASK REG_GENMASK16(13, 7)
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#define CP_PROP(val) REG_FIELD_PREP16(CP_PROP_MASK, val)
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#define V2I_2 2
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#define V2I_MASK REG_GENMASK16(15, 14)
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#define V2I(val) REG_FIELD_PREP16(V2I_MASK, val)
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#define HDMI_DIV_1 1
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#define HDMI_DIV_MASK REG_GENMASK16(2, 0)
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#define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val)
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#endif /* __INTEL_CX0_REG_DEFS_H__ */
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