Files
linux/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml
AngeloGioacchino Del Regno 069862313d dt-bindings: display: mediatek: dpi: Allow specifying resets
Even though the DPI IP has a reset bit on all MediaTek SoCs, it
is optional, and has always been unused until MT8195; specifically:
on older SoCs, like MT8173, the reset bit is located in MMSYS, and
on newer SoCs, like MT8195, it is located in VDOSYS.

For this reason, allow specifying the resets and reset-names on
all MediaTek SoCs.

Those properties are optional because there are multiple ways to
reset this IP and the reset lines in MM/VDO are used only if the
IP cannot perform warm-reset.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-09-26 14:50:43 -05:00

154 lines
3.5 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek DPI and DP_INTF Controller
maintainers:
- CK Hu <ck.hu@mediatek.com>
- Jitao shi <jitao.shi@mediatek.com>
description: |
The MediaTek DPI and DP_INTF function blocks are a sink of the display
subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
parallel output bus.
properties:
compatible:
oneOf:
- enum:
- mediatek,mt2701-dpi
- mediatek,mt7623-dpi
- mediatek,mt8173-dpi
- mediatek,mt8183-dpi
- mediatek,mt8186-dpi
- mediatek,mt8188-dp-intf
- mediatek,mt8192-dpi
- mediatek,mt8195-dp-intf
- mediatek,mt8195-dpi
- items:
- enum:
- mediatek,mt6795-dpi
- const: mediatek,mt8183-dpi
- items:
- enum:
- mediatek,mt8365-dpi
- const: mediatek,mt8192-dpi
- items:
- enum:
- mediatek,mt8188-dpi
- const: mediatek,mt8195-dpi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Pixel Clock
- description: Engine Clock
- description: DPI PLL
clock-names:
items:
- const: pixel
- const: engine
- const: pll
pinctrl-0: true
pinctrl-1: true
pinctrl-names:
items:
- const: default
- const: sleep
power-domains:
description: |
The MediaTek DPI module is typically associated with one of the
following multimedia power domains:
POWER_DOMAIN_DISPLAY
POWER_DOMAIN_VDOSYS
POWER_DOMAIN_MM
The specific power domain used varies depending on the SoC design.
It is recommended to explicitly add the appropriate power domain
property to the DPI node in the device tree.
maxItems: 1
port:
$ref: /schemas/graph.yaml#/properties/port
description:
Output port node. This port should be connected to the input port of an
attached HDMI, LVDS or DisplayPort encoder chip.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: DPI input port
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: DPI output to an HDMI, LVDS or DisplayPort encoder input
required:
- port@0
- port@1
resets:
maxItems: 1
reset-names:
items:
- const: dpi
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
oneOf:
- required:
- port
- required:
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
dpi: dpi@1401d000 {
compatible = "mediatek,mt8173-dpi";
reg = <0x1401d000 0x1000>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DPI_PIXEL>,
<&mmsys CLK_MM_DPI_ENGINE>,
<&apmixedsys CLK_APMIXED_TVDPLL>;
clock-names = "pixel", "engine", "pll";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dpi_pin_func>;
pinctrl-1 = <&dpi_pin_idle>;
port {
dpi0_out: endpoint {
remote-endpoint = <&hdmi0_in>;
};
};
};
...