mirror of
https://github.com/torvalds/linux.git
synced 2026-04-29 12:02:35 -04:00
a19489ca82
The s32g2 and s32g3 NXP platforms have two instances of a Successive Approximation Register ADC. It supports the raw, trigger and scan modes which involves the DMA. Add their descriptions. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
64 lines
1.3 KiB
YAML
64 lines
1.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/iio/adc/nxp,s32g2-sar-adc.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: NXP Successive Approximation ADC
|
|
|
|
description:
|
|
The NXP SAR ADC provides fast and accurate analog-to-digital
|
|
conversion using the Successive Approximation Register (SAR) method.
|
|
It has 12-bit resolution with 8 input channels. Conversions can be
|
|
launched in software or using hardware triggers. It supports
|
|
continuous and one-shot modes with separate registers.
|
|
|
|
maintainers:
|
|
- Daniel Lezcano <daniel.lezcano@kernel.org>
|
|
|
|
properties:
|
|
compatible:
|
|
oneOf:
|
|
- const: nxp,s32g2-sar-adc
|
|
- items:
|
|
- const: nxp,s32g3-sar-adc
|
|
- const: nxp,s32g2-sar-adc
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
maxItems: 1
|
|
|
|
dmas:
|
|
maxItems: 1
|
|
|
|
dma-names:
|
|
const: rx
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupts
|
|
- clocks
|
|
- dmas
|
|
- dma-names
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
adc@401f8000 {
|
|
compatible = "nxp,s32g2-sar-adc";
|
|
reg = <0x401f8000 0x1000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks 0x41>;
|
|
dmas = <&edma0 0 32>;
|
|
dma-names = "rx";
|
|
};
|