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Generally at most 1 blank line is the standard style for DT schema files. Remove the few cases with more than 1 so that the yamllint check for this can be enabled. Acked-by: Lee Jones <lee@kernel.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> # remoteproc Acked-by: Georgi Djakov <djakov@kernel.org> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Andi Shyti <andi.shyti@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Uwe Kleine-König <ukleinek@kernel.org> # for allwinner,sun4i-a10-pwm.yaml Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> # mtd Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> # For PCI controller bindings Link: https://patch.msgid.link/20251023143957.2899600-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
179 lines
4.5 KiB
YAML
179 lines
4.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Amphion VPU codec IP
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maintainers:
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- Ming Qian <ming.qian@nxp.com>
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- Shijie Qin <shijie.qin@nxp.com>
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description: |-
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The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present
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on NXP i.MX8Q SoCs.
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properties:
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$nodename:
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pattern: "^vpu@[0-9a-f]+$"
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compatible:
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items:
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- enum:
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- nxp,imx8qm-vpu
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- nxp,imx8qxp-vpu
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reg:
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maxItems: 1
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power-domains:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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patternProperties:
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"^mailbox@[0-9a-f]+$":
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description:
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Each vpu encoder or decoder correspond a MU, which used for communication
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between driver and firmware. Implement via mailbox on driver.
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$ref: /schemas/mailbox/fsl,mu.yaml#
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"^vpu-core@[0-9a-f]+$":
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description:
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Each core correspond a decoder or encoder, need to configure them
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separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
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has one decoder and one encoder.
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type: object
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properties:
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compatible:
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items:
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- enum:
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- nxp,imx8q-vpu-decoder
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- nxp,imx8q-vpu-encoder
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reg:
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maxItems: 1
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power-domains:
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maxItems: 1
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mbox-names:
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items:
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- const: tx0
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- const: tx1
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- const: rx
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mboxes:
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description:
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List of phandle of 2 MU channels for tx, 1 MU channel for rx.
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maxItems: 3
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memory-region:
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description:
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Phandle to the reserved memory nodes to be associated with the
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remoteproc device. The reserved memory nodes should be carveout nodes,
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and should be defined as per the bindings in
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Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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items:
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- description: region reserved for firmware image sections.
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- description: region used for RPC shared memory between firmware and
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driver.
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required:
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- compatible
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- reg
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- power-domains
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- mbox-names
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- mboxes
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- memory-region
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additionalProperties: false
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required:
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- compatible
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- reg
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- power-domains
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additionalProperties: false
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examples:
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# Device node example for i.MX8QM platform:
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- |
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#include <dt-bindings/firmware/imx/rsrc.h>
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vpu: vpu@2c000000 {
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compatible = "nxp,imx8qm-vpu";
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ranges = <0x2c000000 0x2c000000 0x2000000>;
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reg = <0x2c000000 0x1000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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power-domains = <&pd IMX_SC_R_VPU>;
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mu_m0: mailbox@2d000000 {
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compatible = "fsl,imx6sx-mu";
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reg = <0x2d000000 0x20000>;
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interrupts = <0 472 4>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_VPU_MU_0>;
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};
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mu1_m0: mailbox@2d020000 {
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compatible = "fsl,imx6sx-mu";
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reg = <0x2d020000 0x20000>;
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interrupts = <0 473 4>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_VPU_MU_1>;
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};
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mu2_m0: mailbox@2d040000 {
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compatible = "fsl,imx6sx-mu";
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reg = <0x2d040000 0x20000>;
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interrupts = <0 474 4>;
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#mbox-cells = <2>;
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power-domains = <&pd IMX_SC_R_VPU_MU_2>;
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};
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vpu_core0: vpu-core@2d080000 {
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compatible = "nxp,imx8q-vpu-decoder";
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reg = <0x2d080000 0x10000>;
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power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
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mbox-names = "tx0", "tx1", "rx";
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mboxes = <&mu_m0 0 0>,
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<&mu_m0 0 1>,
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<&mu_m0 1 0>;
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memory-region = <&decoder_boot>, <&decoder_rpc>;
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};
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vpu_core1: vpu-core@2d090000 {
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compatible = "nxp,imx8q-vpu-encoder";
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reg = <0x2d090000 0x10000>;
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power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
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mbox-names = "tx0", "tx1", "rx";
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mboxes = <&mu1_m0 0 0>,
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<&mu1_m0 0 1>,
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<&mu1_m0 1 0>;
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memory-region = <&encoder1_boot>, <&encoder1_rpc>;
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};
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vpu_core2: vpu-core@2d0a0000 {
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reg = <0x2d0a0000 0x10000>;
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compatible = "nxp,imx8q-vpu-encoder";
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power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
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mbox-names = "tx0", "tx1", "rx";
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mboxes = <&mu2_m0 0 0>,
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<&mu2_m0 0 1>,
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<&mu2_m0 1 0>;
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memory-region = <&encoder2_boot>, <&encoder2_rpc>;
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};
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};
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...
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