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LPDDR and DDR bindings are SDRAM types and are likely to share the same properties (at least for density, io-width and reg). To avoid bindings duplication, factorise the properties. The compatible description has been updated because the MR (Mode registers) used to get manufacturer ID and revision ID are not present in case of DDR. Those information should be in a SPD (Serial Presence Detect) EEPROM in case of DIMM module or are known in case of soldered memory chips as they are in the datasheet of the memory chips. Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com> Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-1-a033ac5144da@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
47 lines
1.0 KiB
YAML
47 lines
1.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr5.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: LPDDR5 SDRAM compliant to JEDEC JESD209-5
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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allOf:
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- $ref: jedec,sdram-props.yaml#
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properties:
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compatible:
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items:
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- pattern: "^lpddr5-[0-9a-f]{2},[0-9a-f]{4}$"
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- const: jedec,lpddr5
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serial-id:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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Serial IDs read from Mode Registers 47 through 54. One byte per uint32
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cell (i.e. <MR47 MR48 MR49 MR50 MR51 MR52 MR53 MR54>).
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maxItems: 8
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items:
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minimum: 0
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maximum: 255
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required:
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- compatible
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- density
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- io-width
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unevaluatedProperties: false
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examples:
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- |
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lpddr {
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compatible = "lpddr5-01,0200", "jedec,lpddr5";
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density = <8192>;
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io-width = <8>;
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revision-id = <2 0>;
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serial-id = <3 1 0 0 0 0 0 0>;
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};
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