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0b2333183a
Generally at most 1 blank line is the standard style for DT schema files. Remove the few cases with more than 1 so that the yamllint check for this can be enabled. Acked-by: Lee Jones <lee@kernel.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> # remoteproc Acked-by: Georgi Djakov <djakov@kernel.org> Acked-by: Vinod Koul <vkoul@kernel.org> Acked-by: Andi Shyti <andi.shyti@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Uwe Kleine-König <ukleinek@kernel.org> # for allwinner,sun4i-a10-pwm.yaml Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> # mtd Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> # For PCI controller bindings Link: https://patch.msgid.link/20251023143957.2899600-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
124 lines
3.0 KiB
YAML
124 lines
3.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright (C) 2015, 2019, 2024, Intel Corporation
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/altr,pcie-root-port.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Altera PCIe Root Port
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maintainers:
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- Matthew Gerlach <matthew.gerlach@linux.intel.com>
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properties:
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compatible:
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description: Each family of socfpga has its own implementation of the
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PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5
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family of chips. The Stratix10 family of chips is supported by the
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altr,pcie-root-port-2.0. The Agilex family of chips has three,
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non-register compatible, variants of PCIe Hard IP referred to as the
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F-Tile, P-Tile, and R-Tile, depending on the specific chip instance.
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enum:
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- altr,pcie-root-port-1.0
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- altr,pcie-root-port-2.0
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- altr,pcie-root-port-3.0-f-tile
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- altr,pcie-root-port-3.0-p-tile
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- altr,pcie-root-port-3.0-r-tile
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reg:
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items:
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- description: TX slave port region
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- description: Control register access region
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- description: Hard IP region
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minItems: 2
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reg-names:
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items:
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- const: Txs
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- const: Cra
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- const: Hip
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minItems: 2
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interrupts:
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maxItems: 1
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interrupt-controller: true
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interrupt-map-mask:
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items:
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- const: 0
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- const: 0
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- const: 0
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- const: 7
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interrupt-map:
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maxItems: 4
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"#interrupt-cells":
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const: 1
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msi-parent: true
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- "#interrupt-cells"
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- interrupt-controller
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- interrupt-map
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- interrupt-map-mask
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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- if:
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properties:
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compatible:
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enum:
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- altr,pcie-root-port-1.0
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then:
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properties:
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reg:
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maxItems: 2
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reg-names:
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maxItems: 2
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else:
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properties:
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reg:
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minItems: 3
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reg-names:
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minItems: 3
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pcie_0: pcie@c00000000 {
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compatible = "altr,pcie-root-port-1.0";
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reg = <0xc0000000 0x20000000>,
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<0xff220000 0x00004000>;
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reg-names = "Txs", "Cra";
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interrupt-parent = <&hps_0_arm_gic_0>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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bus-range = <0x0 0xff>;
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device_type = "pci";
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msi-parent = <&msi_to_gic_gen_0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_0 0 0 0 1>,
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<0 0 0 2 &pcie_0 0 0 0 2>,
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<0 0 0 3 &pcie_0 0 0 0 3>,
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<0 0 0 4 &pcie_0 0 0 0 4>;
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ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000>,
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<0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
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};
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