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8a203b0571
Add compatibles for the USB3.0 PHY used in the RZ/V2H(P) and RZ/V2N SoCs. These SoCs integrate the same USB3 PHY IP block as the RZ/G3E, so the RZ/G3E compatible is used as a fallback for both. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://patch.msgid.link/20251222161846.152952-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
71 lines
1.4 KiB
YAML
71 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/renesas,rzg3e-usb3-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G3E USB 3.0 PHY
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maintainers:
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- Biju Das <biju.das.jz@bp.renesas.com>
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properties:
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compatible:
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oneOf:
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- const: renesas,r9a09g047-usb3-phy # RZ/G3E
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- items:
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- enum:
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- renesas,r9a09g056-usb3-phy # RZ/V2N
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- renesas,r9a09g057-usb3-phy # RZ/V2H(P)
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- const: renesas,r9a09g047-usb3-phy
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reg:
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maxItems: 1
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clocks:
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items:
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- description: APB bus clock
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- description: USB 2.0 PHY reference clock
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- description: USB 3.0 PHY reference clock
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clock-names:
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items:
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- const: pclk
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- const: core
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- const: ref_alt_clk_p
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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'#phy-cells':
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- power-domains
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- resets
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- '#phy-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
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usb-phy@15870000 {
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compatible = "renesas,r9a09g047-usb3-phy";
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reg = <0x15870000 0x10000>;
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clocks = <&cpg CPG_MOD 0xb0>, <&cpg CPG_CORE 13>, <&cpg CPG_CORE 12>;
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clock-names = "pclk", "core", "ref_alt_clk_p";
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power-domains = <&cpg>;
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resets = <&cpg 0xaa>;
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#phy-cells = <0>;
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};
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