Files
linux/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
Alex Elder 326a278a36 dt-bindings: phy: spacemit: Introduce PCIe PHY
Add the Device Tree binding for two PCIe PHYs present on the SpacemiT
K1 SoC.  These PHYs are dependent on a separate combo PHY, which
determines at probe time the calibration values used by the PCIe-only
PHYs.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Alex Elder <elder@riscstar.com>
Link: https://lore.kernel.org/all/ba532f8d-a452-40e5-af46-b58b89f70a92@linaro.org/ [1]
Tested-by: Yixun Lan <dlan@gentoo.org>
Link: https://patch.msgid.link/20251218151235.454997-3-elder@riscstar.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-12-23 23:11:03 +05:30

72 lines
1.6 KiB
YAML

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SpacemiT K1 PCIe PHY
maintainers:
- Alex Elder <elder@riscstar.com>
description: >
Two PHYs on the SpacemiT K1 SoC used for only for PCIe. These
PHYs must be configured using calibration values that are
determined by a third "combo PHY". The combo PHY determines
these calibration values during probe so they can be used for
the two PCIe-only PHYs.
The PHY uses an external oscillator as a reference clock. During
normal operation, the PCIe host driver is responsible for ensuring
all other clocks needed by a PHY are enabled, and all resets
affecting the PHY are deasserted.
properties:
compatible:
const: spacemit,k1-pcie-phy
reg:
items:
- description: PHY control registers
clocks:
items:
- description: External oscillator used by the PHY PLL
clock-names:
const: refclk
resets:
items:
- description: PHY reset; remains deasserted after initialization
reset-names:
const: phy
"#phy-cells":
const: 0
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- "#phy-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/spacemit,k1-syscon.h>
phy@c0c10000 {
compatible = "spacemit,k1-pcie-phy";
reg = <0xc0c10000 0x1000>;
clocks = <&vctcxo_24m>;
clock-names = "refclk";
resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
reset-names = "phy";
#phy-cells = <0>;
};