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11659e4c3a
Split out the common memory, CPU and PIC definitions of the simple SMP system to a DTSI file which we will later use for our De0 Nano multicore board device tree. We also take this opportunity to swich underscores to dashes as that seems to be the more common convention for DTS files. Signed-off-by: Stafford Horne <shorne@gmail.com>
69 lines
1.2 KiB
Plaintext
69 lines
1.2 KiB
Plaintext
/ {
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compatible = "opencores,or1ksim";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&pic>;
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aliases {
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uart0 = &serial0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "uart0:115200";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x02000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "opencores,or1200-rtlsvn481";
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reg = <0>;
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};
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cpu1: cpu@1 {
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compatible = "opencores,or1200-rtlsvn481";
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reg = <1>;
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};
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};
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ompic: ompic@98000000 {
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compatible = "openrisc,ompic";
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reg = <0x98000000 16>;
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interrupt-controller;
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#interrupt-cells = <0>;
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interrupts = <1>;
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};
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/*
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* OR1K PIC is built into CPU and accessed via special purpose
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* registers. It is not addressable and, hence, has no 'reg'
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* property.
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*/
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pic: pic {
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compatible = "opencores,or1k-pic-level";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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serial0: serial@90000000 {
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compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
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reg = <0x90000000 0x100>;
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interrupts = <2>;
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};
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enet0: ethoc@92000000 {
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compatible = "opencores,ethoc";
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reg = <0x92000000 0x800>;
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interrupts = <4>;
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big-endian;
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status = "disabled";
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};
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};
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