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d19d963d2a
The suspend routine sets the DPM level to 0, which unintentionally
overwrites the previously saved DPM level. As a result, the device always
resumes with DPM level 0 instead of restoring the original value.
Fix this by ensuring the suspend path does not overwrite the saved DPM
level, allowing the correct DPM level to be restored during resume.
Fixes: f4d7b8a6bc ("accel/amdxdna: Enhance power management settings")
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Lizhi Hou <lizhi.hou@amd.com>
Link: https://patch.msgid.link/20260204171048.3165580-1-lizhi.hou@amd.com
157 lines
3.7 KiB
C
157 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
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*/
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#include <drm/drm_device.h>
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#include <drm/drm_gem_shmem_helper.h>
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#include <drm/drm_print.h>
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#include <drm/gpu_scheduler.h>
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#include <linux/iopoll.h>
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#include "aie2_pci.h"
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#include "amdxdna_pci_drv.h"
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#define SMU_RESULT_OK 1
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/* SMU commands */
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#define AIE2_SMU_POWER_ON 0x3
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#define AIE2_SMU_POWER_OFF 0x4
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#define AIE2_SMU_SET_MPNPUCLK_FREQ 0x5
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#define AIE2_SMU_SET_HCLK_FREQ 0x6
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#define AIE2_SMU_SET_SOFT_DPMLEVEL 0x7
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#define AIE2_SMU_SET_HARD_DPMLEVEL 0x8
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#define NPU4_DPM_TOPS(ndev, dpm_level) \
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({ \
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typeof(ndev) _ndev = ndev; \
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(4096 * (_ndev)->total_col * \
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(_ndev)->priv->dpm_clk_tbl[dpm_level].hclk / 1000000); \
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})
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static int aie2_smu_exec(struct amdxdna_dev_hdl *ndev, u32 reg_cmd,
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u32 reg_arg, u32 *out)
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{
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u32 resp;
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int ret;
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writel(0, SMU_REG(ndev, SMU_RESP_REG));
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writel(reg_arg, SMU_REG(ndev, SMU_ARG_REG));
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writel(reg_cmd, SMU_REG(ndev, SMU_CMD_REG));
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/* Clear and set SMU_INTR_REG to kick off */
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writel(0, SMU_REG(ndev, SMU_INTR_REG));
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writel(1, SMU_REG(ndev, SMU_INTR_REG));
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ret = readx_poll_timeout(readl, SMU_REG(ndev, SMU_RESP_REG), resp,
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resp, AIE2_INTERVAL, AIE2_TIMEOUT);
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if (ret) {
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XDNA_ERR(ndev->xdna, "smu cmd %d timed out", reg_cmd);
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return ret;
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}
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if (out)
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*out = readl(SMU_REG(ndev, SMU_OUT_REG));
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if (resp != SMU_RESULT_OK) {
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XDNA_ERR(ndev->xdna, "smu cmd %d failed, 0x%x", reg_cmd, resp);
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return -EINVAL;
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}
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return 0;
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}
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int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
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{
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u32 freq;
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int ret;
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ret = aie2_smu_exec(ndev, AIE2_SMU_SET_MPNPUCLK_FREQ,
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ndev->priv->dpm_clk_tbl[dpm_level].npuclk, &freq);
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if (ret) {
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XDNA_ERR(ndev->xdna, "Set npu clock to %d failed, ret %d\n",
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ndev->priv->dpm_clk_tbl[dpm_level].npuclk, ret);
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return ret;
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}
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ndev->npuclk_freq = freq;
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ret = aie2_smu_exec(ndev, AIE2_SMU_SET_HCLK_FREQ,
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ndev->priv->dpm_clk_tbl[dpm_level].hclk, &freq);
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if (ret) {
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XDNA_ERR(ndev->xdna, "Set h clock to %d failed, ret %d\n",
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ndev->priv->dpm_clk_tbl[dpm_level].hclk, ret);
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return ret;
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}
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ndev->hclk_freq = freq;
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ndev->max_tops = 2 * ndev->total_col;
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ndev->curr_tops = ndev->max_tops * freq / 1028;
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XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n",
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ndev->npuclk_freq, ndev->hclk_freq);
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return 0;
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}
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int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
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{
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int ret;
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ret = aie2_smu_exec(ndev, AIE2_SMU_SET_HARD_DPMLEVEL, dpm_level, NULL);
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if (ret) {
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XDNA_ERR(ndev->xdna, "Set hard dpm level %d failed, ret %d ",
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dpm_level, ret);
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return ret;
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}
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ret = aie2_smu_exec(ndev, AIE2_SMU_SET_SOFT_DPMLEVEL, dpm_level, NULL);
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if (ret) {
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XDNA_ERR(ndev->xdna, "Set soft dpm level %d failed, ret %d",
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dpm_level, ret);
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return ret;
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}
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ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
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ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
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ndev->max_tops = NPU4_DPM_TOPS(ndev, ndev->max_dpm_level);
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ndev->curr_tops = NPU4_DPM_TOPS(ndev, dpm_level);
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XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n",
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ndev->npuclk_freq, ndev->hclk_freq);
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return 0;
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}
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int aie2_smu_init(struct amdxdna_dev_hdl *ndev)
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{
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int ret;
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/*
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* Failing to set power off indicates an unrecoverable hardware or
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* firmware error.
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*/
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ret = aie2_smu_exec(ndev, AIE2_SMU_POWER_OFF, 0, NULL);
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if (ret) {
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XDNA_ERR(ndev->xdna, "Access power failed, ret %d", ret);
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return ret;
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}
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ret = aie2_smu_exec(ndev, AIE2_SMU_POWER_ON, 0, NULL);
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if (ret) {
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XDNA_ERR(ndev->xdna, "Power on failed, ret %d", ret);
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return ret;
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}
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return 0;
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}
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void aie2_smu_fini(struct amdxdna_dev_hdl *ndev)
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{
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int ret;
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ndev->priv->hw_ops.set_dpm(ndev, 0);
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ret = aie2_smu_exec(ndev, AIE2_SMU_POWER_OFF, 0, NULL);
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if (ret)
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XDNA_ERR(ndev->xdna, "Power off failed, ret %d", ret);
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}
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