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bf4afc53b7
This was done entirely with mindless brute force, using
git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'
to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.
Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.
For the same reason the 'flex' versions will be done as a separate
conversion.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
114 lines
3.1 KiB
C
114 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2013 Emilio López
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* Emilio López <emilio@elopez.com.ar>
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*
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* Copyright 2013 Chen-Yu Tsai
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* Chen-Yu Tsai <wens@csie.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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static DEFINE_SPINLOCK(gmac_lock);
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#define SUN7I_A20_GMAC_GPIT 2
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#define SUN7I_A20_GMAC_MASK 0x3
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#define SUN7I_A20_GMAC_PARENTS 2
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static u32 sun7i_a20_gmac_mux_table[SUN7I_A20_GMAC_PARENTS] = {
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0x00, /* Select mii_phy_tx_clk */
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0x02, /* Select gmac_int_tx_clk */
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};
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/**
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* sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
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* @node: &struct device_node for the clock
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*
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* This clock looks something like this
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* ________________________
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* MII TX clock from PHY >-----|___________ _________|----> to GMAC core
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* GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
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* Ext. 125MHz RGMII TX clk >--|__divider__/ |
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* |________________________|
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*
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* The external 125 MHz reference is optional, i.e. GMAC can use its
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* internal TX clock just fine. The A31 GMAC clock module does not have
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* the divider controls for the external reference.
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*
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* To keep it simple, let the GMAC use either the MII TX clock for MII mode,
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* and its internal TX clock for GMII and RGMII modes. The GMAC driver should
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* select the appropriate source and gate/ungate the output to the PHY.
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*
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* Only the GMAC should use this clock. Altering the clock so that it doesn't
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* match the GMAC's operation parameters will result in the GMAC not being
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* able to send traffic out. The GMAC driver should set the clock rate and
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* enable/disable this clock to configure the required state. The clock
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* driver then responds by auto-reparenting the clock.
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*/
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static void __init sun7i_a20_gmac_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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struct clk_mux *mux;
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struct clk_gate *gate;
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const char *clk_name = node->name;
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const char *parents[SUN7I_A20_GMAC_PARENTS];
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void __iomem *reg;
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if (of_property_read_string(node, "clock-output-names", &clk_name))
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return;
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/* allocate mux and gate clock structs */
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mux = kzalloc_obj(struct clk_mux);
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if (!mux)
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return;
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gate = kzalloc_obj(struct clk_gate);
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if (!gate)
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goto free_mux;
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/* gmac clock requires exactly 2 parents */
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if (of_clk_parent_fill(node, parents, 2) != 2)
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goto free_gate;
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reg = of_iomap(node, 0);
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if (!reg)
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goto free_gate;
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/* set up gate and fixed rate properties */
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gate->reg = reg;
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gate->bit_idx = SUN7I_A20_GMAC_GPIT;
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gate->lock = &gmac_lock;
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mux->reg = reg;
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mux->mask = SUN7I_A20_GMAC_MASK;
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mux->table = sun7i_a20_gmac_mux_table;
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mux->lock = &gmac_lock;
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clk = clk_register_composite(NULL, clk_name,
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parents, SUN7I_A20_GMAC_PARENTS,
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&mux->hw, &clk_mux_ops,
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NULL, NULL,
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&gate->hw, &clk_gate_ops,
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0);
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if (IS_ERR(clk))
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goto iounmap_reg;
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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return;
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iounmap_reg:
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iounmap(reg);
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free_gate:
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kfree(gate);
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free_mux:
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kfree(mux);
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}
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CLK_OF_DECLARE(sun7i_a20_gmac, "allwinner,sun7i-a20-gmac-clk",
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sun7i_a20_gmac_clk_setup);
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