Paul Hsieh 2e72fdba8a drm/amd/display: update dpp/disp clock from smu clock table ...

[Why]
The reason some high-resolution monitors fail to display properly
is that this platform does not support sufficiently high DPP and
DISP clock frequencies

[How]
Update DISP and DPP clocks from the smu clock table then DML can
filter these mode if not support.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2025-08-04 14:38:59 -04:00

..

dcn301_smu.c

drm/amd/display: Add SMU timeout check and retry

2024-02-22 10:14:53 -05:00

dcn301_smu.h

…

vg_clk_mgr.c

drm/amd/display: update dpp/disp clock from smu clock table

2025-08-04 14:38:59 -04:00

vg_clk_mgr.h

drm/amd/display: move FPU code from dcn301 clk mgr to DML folder

2022-07-25 09:31:05 -04:00