Charlene Liu cb7a978c7c drm/amd/display: DPP low mem pwr related adjustment -Part I ...

[why]
Default low pwr mem state get chagned.
SW needs to wake mem up first
also need to put back to LS again after use: will do in Part II.

Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2025-12-16 13:26:06 -05:00

..

dcn10_dpp_cm.c

drm/amd/display: Remove unnecessary call to REG_SEQ_SUBMIT|WAIT_DONE

2024-08-13 12:12:51 -04:00

dcn10_dpp_dscl.c

drm/amd/display: Refactor DPP into a component directory

2024-03-20 13:37:37 -04:00

dcn10_dpp.c

drm/amd/display: Driver implementation for cursor offloading to DMU

2025-10-13 14:14:32 -04:00

dcn10_dpp.h

drm/amd/display: DPP low mem pwr related adjustment -Part I

2025-12-16 13:26:06 -05:00