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4c595e7511
[Why] Direct DCCG register access in hwseq layer was creating register conflicts. [How] Migrated DCCG registers from hwseq-dccg component. Reviewed-by: Martin Leung <Martin.Leung@amd.com> Signed-off-by: Bhuvanachandra Pinninti <BhuvanaChandra.Pinninti@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
344 lines
9.8 KiB
C
344 lines
9.8 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_DCCG_H__
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#define __DAL_DCCG_H__
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#include "dc_types.h"
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#include "hw_shared.h"
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enum phyd32clk_clock_source {
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PHYD32CLKA,
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PHYD32CLKB,
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PHYD32CLKC,
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PHYD32CLKD,
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PHYD32CLKE,
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PHYD32CLKF,
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PHYD32CLKG,
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};
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enum physymclk_clock_source {
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PHYSYMCLK_FORCE_SRC_SYMCLK, // Select symclk as source of clock which is output to PHY through DCIO.
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PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO.
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PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO.
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};
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enum streamclk_source {
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REFCLK, // Selects REFCLK as source for hdmistreamclk.
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DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk.
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DPREFCLK, // Selects DPREFCLK as source for hdmistreamclk
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};
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enum dentist_dispclk_change_mode {
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DISPCLK_CHANGE_MODE_IMMEDIATE,
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DISPCLK_CHANGE_MODE_RAMPING,
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};
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struct dp_dto_params {
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int otg_inst;
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enum signal_type signal;
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enum streamclk_source clk_src;
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uint64_t pixclk_hz;
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uint64_t refclk_hz;
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};
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enum pixel_rate_div {
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PIXEL_RATE_DIV_BY_1 = 0,
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PIXEL_RATE_DIV_BY_2 = 1,
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PIXEL_RATE_DIV_BY_4 = 3,
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PIXEL_RATE_DIV_NA = 0xF
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};
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struct dcn_dccg_reg_state {
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uint32_t dc_mem_global_pwr_req_cntl;
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uint32_t dccg_audio_dtbclk_dto_modulo;
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uint32_t dccg_audio_dtbclk_dto_phase;
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uint32_t dccg_audio_dto_source;
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uint32_t dccg_audio_dto0_module;
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uint32_t dccg_audio_dto0_phase;
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uint32_t dccg_audio_dto1_module;
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uint32_t dccg_audio_dto1_phase;
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uint32_t dccg_cac_status;
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uint32_t dccg_cac_status2;
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uint32_t dccg_disp_cntl_reg;
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uint32_t dccg_ds_cntl;
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uint32_t dccg_ds_dto_incr;
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uint32_t dccg_ds_dto_modulo;
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uint32_t dccg_ds_hw_cal_interval;
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uint32_t dccg_gate_disable_cntl;
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uint32_t dccg_gate_disable_cntl2;
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uint32_t dccg_gate_disable_cntl3;
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uint32_t dccg_gate_disable_cntl4;
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uint32_t dccg_gate_disable_cntl5;
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uint32_t dccg_gate_disable_cntl6;
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uint32_t dccg_global_fgcg_rep_cntl;
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uint32_t dccg_gtc_cntl;
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uint32_t dccg_gtc_current;
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uint32_t dccg_gtc_dto_incr;
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uint32_t dccg_gtc_dto_modulo;
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uint32_t dccg_perfmon_cntl;
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uint32_t dccg_perfmon_cntl2;
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uint32_t dccg_soft_reset;
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uint32_t dccg_test_clk_sel;
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uint32_t dccg_vsync_cnt_ctrl;
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uint32_t dccg_vsync_cnt_int_ctrl;
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uint32_t dccg_vsync_otg0_latch_value;
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uint32_t dccg_vsync_otg1_latch_value;
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uint32_t dccg_vsync_otg2_latch_value;
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uint32_t dccg_vsync_otg3_latch_value;
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uint32_t dccg_vsync_otg4_latch_value;
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uint32_t dccg_vsync_otg5_latch_value;
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uint32_t dispclk_cgtt_blk_ctrl_reg;
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uint32_t dispclk_freq_change_cntl;
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uint32_t dp_dto_dbuf_en;
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uint32_t dp_dto0_modulo;
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uint32_t dp_dto0_phase;
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uint32_t dp_dto1_modulo;
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uint32_t dp_dto1_phase;
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uint32_t dp_dto2_modulo;
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uint32_t dp_dto2_phase;
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uint32_t dp_dto3_modulo;
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uint32_t dp_dto3_phase;
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uint32_t dpiaclk_540m_dto_modulo;
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uint32_t dpiaclk_540m_dto_phase;
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uint32_t dpiaclk_810m_dto_modulo;
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uint32_t dpiaclk_810m_dto_phase;
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uint32_t dpiaclk_dto_cntl;
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uint32_t dpiasymclk_cntl;
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uint32_t dppclk_cgtt_blk_ctrl_reg;
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uint32_t dppclk_ctrl;
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uint32_t dppclk_dto_ctrl;
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uint32_t dppclk0_dto_param;
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uint32_t dppclk1_dto_param;
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uint32_t dppclk2_dto_param;
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uint32_t dppclk3_dto_param;
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uint32_t dprefclk_cgtt_blk_ctrl_reg;
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uint32_t dprefclk_cntl;
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uint32_t dpstreamclk_cntl;
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uint32_t dscclk_dto_ctrl;
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uint32_t dscclk0_dto_param;
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uint32_t dscclk1_dto_param;
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uint32_t dscclk2_dto_param;
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uint32_t dscclk3_dto_param;
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uint32_t dtbclk_dto_dbuf_en;
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uint32_t dtbclk_dto0_modulo;
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uint32_t dtbclk_dto0_phase;
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uint32_t dtbclk_dto1_modulo;
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uint32_t dtbclk_dto1_phase;
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uint32_t dtbclk_dto2_modulo;
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uint32_t dtbclk_dto2_phase;
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uint32_t dtbclk_dto3_modulo;
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uint32_t dtbclk_dto3_phase;
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uint32_t dtbclk_p_cntl;
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uint32_t force_symclk_disable;
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uint32_t hdmicharclk0_clock_cntl;
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uint32_t hdmistreamclk_cntl;
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uint32_t hdmistreamclk0_dto_param;
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uint32_t microsecond_time_base_div;
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uint32_t millisecond_time_base_div;
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uint32_t otg_pixel_rate_div;
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uint32_t otg0_phypll_pixel_rate_cntl;
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uint32_t otg0_pixel_rate_cntl;
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uint32_t otg1_phypll_pixel_rate_cntl;
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uint32_t otg1_pixel_rate_cntl;
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uint32_t otg2_phypll_pixel_rate_cntl;
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uint32_t otg2_pixel_rate_cntl;
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uint32_t otg3_phypll_pixel_rate_cntl;
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uint32_t otg3_pixel_rate_cntl;
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uint32_t phyasymclk_clock_cntl;
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uint32_t phybsymclk_clock_cntl;
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uint32_t phycsymclk_clock_cntl;
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uint32_t phydsymclk_clock_cntl;
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uint32_t phyesymclk_clock_cntl;
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uint32_t phyplla_pixclk_resync_cntl;
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uint32_t phypllb_pixclk_resync_cntl;
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uint32_t phypllc_pixclk_resync_cntl;
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uint32_t phyplld_pixclk_resync_cntl;
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uint32_t phyplle_pixclk_resync_cntl;
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uint32_t refclk_cgtt_blk_ctrl_reg;
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uint32_t socclk_cgtt_blk_ctrl_reg;
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uint32_t symclk_cgtt_blk_ctrl_reg;
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uint32_t symclk_psp_cntl;
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uint32_t symclk32_le_cntl;
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uint32_t symclk32_se_cntl;
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uint32_t symclka_clock_enable;
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uint32_t symclkb_clock_enable;
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uint32_t symclkc_clock_enable;
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uint32_t symclkd_clock_enable;
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uint32_t symclke_clock_enable;
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};
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struct dccg {
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struct dc_context *ctx;
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const struct dccg_funcs *funcs;
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int pipe_dppclk_khz[MAX_PIPES];
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int ref_dppclk;
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bool dpp_clock_gated[MAX_PIPES];
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//int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */
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//int audio_dtbclk_khz;/* TODO needs to be removed */
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//int ref_dtbclk_khz;/* TODO needs to be removed */
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};
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struct dtbclk_dto_params {
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const struct dc_crtc_timing *timing;
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int otg_inst;
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int pixclk_khz;
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int req_audio_dtbclk_khz;
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int num_odm_segments;
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int ref_dtbclk_khz;
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bool is_hdmi;
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};
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struct dccg_funcs {
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void (*update_dpp_dto)(struct dccg *dccg,
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int dpp_inst,
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int req_dppclk);
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void (*get_dccg_ref_freq)(struct dccg *dccg,
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unsigned int xtalin_freq_inKhz,
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unsigned int *dccg_ref_freq_inKhz);
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void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
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bool en);
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void (*otg_add_pixel)(struct dccg *dccg,
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uint32_t otg_inst);
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void (*otg_drop_pixel)(struct dccg *dccg,
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uint32_t otg_inst);
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void (*dccg_init)(struct dccg *dccg);
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void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */
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void (*allow_clock_gating)(struct dccg *dccg, bool allow);
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void (*enable_memory_low_power)(struct dccg *dccg, bool enable);
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bool (*is_s0i3_golden_init_wa_done)(struct dccg *dccg);
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void (*set_dpstreamclk_root_clock_gating)(
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struct dccg *dccg,
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int dp_hpo_inst,
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bool enable);
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void (*set_dpstreamclk)(
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struct dccg *dccg,
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enum streamclk_source src,
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int otg_inst,
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int dp_hpo_inst);
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void (*enable_symclk32_se)(
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struct dccg *dccg,
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int hpo_se_inst,
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enum phyd32clk_clock_source phyd32clk);
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void (*disable_symclk32_se)(
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struct dccg *dccg,
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int hpo_se_inst);
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void (*enable_symclk32_le)(
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struct dccg *dccg,
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int hpo_le_inst,
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enum phyd32clk_clock_source phyd32clk);
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void (*disable_symclk32_le)(
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struct dccg *dccg,
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int hpo_le_inst);
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void (*set_symclk32_le_root_clock_gating)(
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struct dccg *dccg,
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int hpo_le_inst,
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bool enable);
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void (*set_physymclk)(
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struct dccg *dccg,
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int phy_inst,
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enum physymclk_clock_source clk_src,
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bool force_enable);
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void (*set_physymclk_root_clock_gating)(
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struct dccg *dccg,
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int phy_inst,
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bool enable);
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void (*set_dtbclk_dto)(
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struct dccg *dccg,
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const struct dtbclk_dto_params *params);
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void (*set_audio_dtbclk_dto)(
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struct dccg *dccg,
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const struct dtbclk_dto_params *params);
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void (*set_dispclk_change_mode)(
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struct dccg *dccg,
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enum dentist_dispclk_change_mode change_mode);
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void (*disable_dsc)(
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struct dccg *dccg,
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int inst);
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void (*enable_dsc)(
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struct dccg *dccg,
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int inst);
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void (*set_pixel_rate_div)(struct dccg *dccg,
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uint32_t otg_inst,
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enum pixel_rate_div k1,
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enum pixel_rate_div k2);
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void (*get_pixel_rate_div)(struct dccg *dccg,
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uint32_t otg_inst,
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uint32_t *div_factor1,
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uint32_t *div_factor2);
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void (*set_valid_pixel_rate)(
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struct dccg *dccg,
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int ref_dtbclk_khz,
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int otg_inst,
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int pixclk_khz);
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void (*trigger_dio_fifo_resync)(
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struct dccg *dccg);
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void (*dpp_root_clock_control)(
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struct dccg *dccg,
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unsigned int dpp_inst,
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bool clock_on);
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void (*enable_symclk_se)(
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struct dccg *dccg,
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uint32_t stream_enc_inst,
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uint32_t link_enc_inst);
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void (*disable_symclk_se)(
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struct dccg *dccg,
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uint32_t stream_enc_inst,
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uint32_t link_enc_inst);
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void (*set_dp_dto)(
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struct dccg *dccg,
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const struct dp_dto_params *params);
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void (*set_dtbclk_p_src)(
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struct dccg *dccg,
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enum streamclk_source src,
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uint32_t otg_inst);
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void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst, uint32_t num_slices_h);
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void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);
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void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);
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void (*dccg_read_reg_state)(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state);
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void (*dccg_enable_global_fgcg)(struct dccg *dccg, bool enable);
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};
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#endif //__DAL_DCCG_H__
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