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32a92f8c89
This converts some of the visually simpler cases that have been split over multiple lines. I only did the ones that are easy to verify the resulting diff by having just that final GFP_KERNEL argument on the next line. Somebody should probably do a proper coccinelle script for this, but for me the trivial script actually resulted in an assertion failure in the middle of the script. I probably had made it a bit _too_ trivial. So after fighting that far a while I decided to just do some of the syntactically simpler cases with variations of the previous 'sed' scripts. The more syntactically complex multi-line cases would mostly really want whitespace cleanup anyway. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
224 lines
6.7 KiB
C
224 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2025 Etnaviv Project
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*/
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#include <linux/errno.h>
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#include <linux/dev_printk.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include "etnaviv_buffer.h"
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#include "etnaviv_cmdbuf.h"
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#include "etnaviv_gpu.h"
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#include "state_3d.xml.h"
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#include "etnaviv_flop_reset.h"
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static int etnaviv_force_flop_reset;
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module_param_named(force_flop_reset, etnaviv_force_flop_reset, int, 0);
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#define PPU_IMAGE_STRIDE 64
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#define PPU_IMAGE_XSIZE 64
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#define PPU_IMAGE_YSIZE 6
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#define PPU_FLOP_RESET_INSTR_DWORD_COUNT 16
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static void etnaviv_emit_flop_reset_state_ppu(struct etnaviv_cmdbuf *cmdbuf,
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u32 buffer_base, u32 input_offset,
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u32 output_offset,
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u32 shader_offset,
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u32 shader_size,
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u32 shader_register_count)
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{
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CMD_LOAD_STATE(cmdbuf, VIVS_GL_API_MODE, VIVS_GL_API_MODE_OPENCL);
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CMD_SEM(cmdbuf, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_STALL(cmdbuf, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
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CMD_LOAD_STATES_START(cmdbuf, VIVS_SH_HALTI5_UNIFORMS(0), 4);
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OUT(cmdbuf, buffer_base + input_offset);
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OUT(cmdbuf, PPU_IMAGE_STRIDE);
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OUT(cmdbuf, PPU_IMAGE_XSIZE | (PPU_IMAGE_YSIZE << 16));
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OUT(cmdbuf, 0x444051f0);
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OUT(cmdbuf, 0xffffffff);
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CMD_LOAD_STATES_START(cmdbuf, VIVS_SH_HALTI5_UNIFORMS(4), 4);
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OUT(cmdbuf, buffer_base + output_offset);
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OUT(cmdbuf, PPU_IMAGE_STRIDE);
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OUT(cmdbuf, PPU_IMAGE_XSIZE | (PPU_IMAGE_YSIZE << 16));
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OUT(cmdbuf, 0x444051f0);
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OUT(cmdbuf, 0xffffffff);
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CMD_LOAD_STATE(cmdbuf, VIVS_CL_CONFIG,
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VIVS_CL_CONFIG_DIMENSIONS(2) |
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VIVS_CL_CONFIG_VALUE_ORDER(3));
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CMD_LOAD_STATE(cmdbuf, VIVS_VS_ICACHE_INVALIDATE, 0x1f);
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CMD_LOAD_STATE(cmdbuf, VIVS_PS_VARYING_NUM_COMPONENTS(0), 0);
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CMD_LOAD_STATE(cmdbuf, VIVS_PS_TEMP_REGISTER_CONTROL,
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shader_register_count);
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CMD_LOAD_STATE(cmdbuf, VIVS_PS_SAMPLER_BASE, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_PS_UNIFORM_BASE, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_PS_NEWRANGE_LOW, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_PS_NEWRANGE_HIGH, shader_size / 16);
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CMD_LOAD_STATE(cmdbuf, VIVS_PS_INST_ADDR, buffer_base + shader_offset);
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CMD_LOAD_STATE(cmdbuf, VIVS_SH_CONFIG, VIVS_SH_CONFIG_RTNE_ROUNDING);
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CMD_LOAD_STATE(cmdbuf, VIVS_VS_ICACHE_CONTROL,
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VIVS_VS_ICACHE_CONTROL_ENABLE);
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CMD_LOAD_STATE(cmdbuf, VIVS_PS_ICACHE_COUNT, shader_size / 16 - 1);
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CMD_LOAD_STATE(cmdbuf, VIVS_PS_INPUT_COUNT, 0x1f01);
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CMD_LOAD_STATE(cmdbuf, VIVS_VS_HALTI5_UNK008A0, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_PA_VS_OUTPUT_COUNT, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_GL_VARYING_TOTAL_COMPONENTS, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_PS_CONTROL_EXT, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_VS_OUTPUT_COUNT, 0x1);
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CMD_LOAD_STATE(cmdbuf, VIVS_GL_HALTI5_SH_SPECIALS, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_PS_ICACHE_PREFETCH, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_CL_UNK00924, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_CL_THREAD_ALLOCATION, 0x1);
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CMD_LOAD_STATE(cmdbuf, VIVS_CL_GLOBAL_WORK_OFFSET_X, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_CL_GLOBAL_WORK_OFFSET_Y, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_CL_GLOBAL_WORK_OFFSET_Z, 0x0);
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CMD_LOAD_STATES_START(cmdbuf, VIVS_CL_WORKGROUP_COUNT_X, 9);
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OUT(cmdbuf, 0xf);
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OUT(cmdbuf, 0x5);
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OUT(cmdbuf, 0xffffffff);
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OUT(cmdbuf, 0x0);
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OUT(cmdbuf, 0x0);
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OUT(cmdbuf, 0x3ff);
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OUT(cmdbuf, 0x0);
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OUT(cmdbuf, 0x4);
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OUT(cmdbuf, 0x1);
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OUT(cmdbuf, 0x0);
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CMD_LOAD_STATE(cmdbuf, VIVS_CL_KICKER, 0xbadabeeb);
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CMD_LOAD_STATE(cmdbuf, VIVS_GL_FLUSH_CACHE,
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VIVS_GL_FLUSH_CACHE_SHADER_L1 |
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VIVS_GL_FLUSH_CACHE_UNK10 |
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VIVS_GL_FLUSH_CACHE_UNK11);
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}
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static void etnaviv_flop_reset_ppu_fill_input(u32 *buffer, u32 size)
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{
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memset32(buffer, 0x01010101, size / 4);
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}
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static void etnaviv_flop_reset_ppu_set_shader(u8 *dest)
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{
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static const u32 inst[PPU_FLOP_RESET_INSTR_DWORD_COUNT] = {
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/* img_load.u8 r1, c0, r0.xy */
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0x78011779,
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0x39000804,
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0x00A90050,
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0x00000000,
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/* img_load.u8 r2, c0, r0.xy */
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0x78021779,
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0x39000804,
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0x00A90050,
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0x00000000,
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/* dp2x8 r1, r1, r2, c3_512 */
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0xB8017145,
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0x390018FC,
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0x01C90140,
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0x40390028,
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/* img_store.u8 r1, c2, r0.xy, r1 */
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0x380007BA,
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0x39001804,
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0x00A90050,
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0x00390018,
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};
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memcpy(dest, inst, sizeof(inst));
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}
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static const struct etnaviv_flop_reset_entry {
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u16 chip_model;
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u16 revision;
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u32 flags;
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} etnaviv_flop_reset_db[] = {
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{
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.chip_model = 0x8000,
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.revision = 0x6205,
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},
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};
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bool etnaviv_flop_reset_ppu_require(const struct etnaviv_chip_identity *chip_id)
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{
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const struct etnaviv_flop_reset_entry *e = etnaviv_flop_reset_db;
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for (int i = 0; i < ARRAY_SIZE(etnaviv_flop_reset_db); ++i, ++e) {
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if (chip_id->model == e->chip_model &&
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chip_id->revision == e->revision)
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return true;
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}
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if (etnaviv_force_flop_reset) {
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if (!(chip_id->features & chipFeatures_PIPE_3D)) {
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pr_warn("Etnaviv: model: 0x%04x, revision: 0x%04x does not support PIPE_3D\n",
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chip_id->model, chip_id->revision);
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pr_warn("Request to force PPU flop reset ignored.\n");
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return false;
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}
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pr_info("Force PPU flop reset for model: 0x%04x, revision: 0x%04x\n",
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chip_id->model, chip_id->revision);
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return true;
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}
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return false;
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}
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static const u32 image_data_size = PPU_IMAGE_STRIDE * PPU_IMAGE_YSIZE;
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static const u32 output_offset = ALIGN(image_data_size, 64);
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static const u32 shader_offset = ALIGN(output_offset + image_data_size, 64);
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static const u32 shader_size = PPU_FLOP_RESET_INSTR_DWORD_COUNT * sizeof(u32);
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static const u32 shader_register_count = 3;
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static const u32 buffer_size = shader_offset + shader_size;
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int etnaviv_flop_reset_ppu_init(struct etnaviv_drm_private *priv)
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{
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/* Get some space from the ring buffer to put the payload
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* (input and output image, and shader), we keep this buffer
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* for the whole life time the driver is bound
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*/
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priv->flop_reset_data_ppu = kzalloc_obj(*priv->flop_reset_data_ppu);
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if (!priv->flop_reset_data_ppu)
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return -ENOMEM;
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int ret = etnaviv_cmdbuf_init(priv->cmdbuf_suballoc,
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priv->flop_reset_data_ppu, buffer_size);
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if (ret) {
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kfree(priv->flop_reset_data_ppu);
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return ret;
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}
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void *buffer_base = priv->flop_reset_data_ppu->vaddr;
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u32 *input_data = (u32 *)buffer_base;
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u8 *shader_data = (u8 *)buffer_base + shader_offset;
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etnaviv_flop_reset_ppu_fill_input(input_data, image_data_size);
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etnaviv_flop_reset_ppu_set_shader(shader_data);
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return 0;
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}
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void etnaviv_flop_reset_ppu_run(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_drm_private *priv = gpu->drm->dev_private;
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if (!priv->flop_reset_data_ppu) {
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dev_err(gpu->dev,
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"Oops: Flop reset data was not initialized, skipping\n");
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return;
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}
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u32 buffer_base = etnaviv_cmdbuf_get_va(priv->flop_reset_data_ppu,
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&gpu->mmu_context->cmdbuf_mapping);
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etnaviv_emit_flop_reset_state_ppu(&gpu->buffer, buffer_base, 0,
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output_offset, shader_offset,
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shader_size, shader_register_count);
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}
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