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3906e7a3b2
The issue is that drm_connector_helper_detect_from_ddc() returns wrong
status when plugging or unplugging the monitor, which may cause the link
failed err.[0] Use HPD pin status in DP's detect_ctx() for real physical
monitor in/out, and implement a complete DP detection including read DPCD,
check if it's a branch device and its sink count for different situations.
[0]:
hibme-drm 0000:83:00.0: [drm] *ERROR* channel equalization failed 5 times
hibme-drm 0000:83:00.0: [drm] *ERROR* channel equalization failed 5 times
hibme-drm 0000:83:00.0: [drm] *ERROR* dp link training failed, ret: -16
hibmc-drm 0000:83:00.0: [drm] *ERROR* hibme dp mode set failed: -16
Fixes: 3c7623fb5b ("drm/hisilicon/hibmc: Enable this hot plug detect of irq feature")
Signed-off-by: Baihan Li <libaihan@huawei.com>
Signed-off-by: Yongbang Shi <shiyongbang@huawei.com>
Reviewed-by: Tao Tian <tiantao6@hisilicon.com>
Link: https://patch.msgid.link/20251210023759.3944834-2-shiyongbang@huawei.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
136 lines
4.3 KiB
C
136 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Copyright (c) 2024 Hisilicon Limited. */
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#ifndef DP_REG_H
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#define DP_REG_H
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#define HIBMC_DP_AUX_CMD_ADDR 0x50
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#define HIBMC_DP_AUX_WR_DATA0 0x54
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#define HIBMC_DP_AUX_WR_DATA1 0x58
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#define HIBMC_DP_AUX_WR_DATA2 0x5c
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#define HIBMC_DP_AUX_WR_DATA3 0x60
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#define HIBMC_DP_AUX_RD_DATA0 0x64
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#define HIBMC_DP_AUX_REQ 0x74
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#define HIBMC_DP_CFG_AUX_REQ BIT(0)
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#define HIBMC_DP_CFG_AUX_SYNC_LEN_SEL BIT(1)
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#define HIBMC_DP_CFG_AUX_TIMER_TIMEOUT BIT(2)
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#define HIBMC_DP_CFG_AUX_MIN_PULSE_NUM GENMASK(13, 9)
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#define HIBMC_DP_AUX_STATUS 0x78
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#define HIBMC_DP_CFG_AUX_TIMEOUT BIT(0)
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#define HIBMC_DP_CFG_AUX_STATUS GENMASK(11, 4)
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#define HIBMC_DP_CFG_AUX_READY_DATA_BYTE GENMASK(16, 12)
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#define HIBMC_DP_CFG_AUX GENMASK(24, 17)
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#define HIBMC_DP_HPD_STATUS 0x98
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#define HIBMC_DP_HPD_CUR_STATE GENMASK(7, 4)
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#define HIBMC_DP_PHYIF_CTRL0 0xa0
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#define HIBMC_DP_CFG_SCRAMBLE_EN BIT(0)
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#define HIBMC_DP_CFG_PAT_SEL GENMASK(7, 4)
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#define HIBMC_DP_CFG_LANE_DATA_EN GENMASK(11, 8)
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#define HIBMC_DP_VIDEO_CTRL 0x100
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#define HIBMC_DP_CFG_STREAM_RGB_ENABLE BIT(1)
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#define HIBMC_DP_CFG_STREAM_VIDEO_MAPPING GENMASK(5, 2)
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#define HIBMC_DP_CFG_STREAM_FRAME_MODE BIT(6)
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#define HIBMC_DP_CFG_STREAM_HSYNC_POLARITY BIT(7)
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#define HIBMC_DP_CFG_STREAM_VSYNC_POLARITY BIT(8)
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#define HIBMC_DP_VIDEO_CONFIG0 0x104
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#define HIBMC_DP_CFG_STREAM_HACTIVE GENMASK(31, 16)
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#define HIBMC_DP_CFG_STREAM_HBLANK GENMASK(15, 0)
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#define HIBMC_DP_VIDEO_CONFIG1 0x108
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#define HIBMC_DP_CFG_STREAM_VACTIVE GENMASK(31, 16)
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#define HIBMC_DP_CFG_STREAM_VBLANK GENMASK(15, 0)
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#define HIBMC_DP_VIDEO_CONFIG2 0x10c
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#define HIBMC_DP_CFG_STREAM_HSYNC_WIDTH GENMASK(15, 0)
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#define HIBMC_DP_VIDEO_CONFIG3 0x110
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#define HIBMC_DP_CFG_STREAM_VSYNC_WIDTH GENMASK(15, 0)
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#define HIBMC_DP_CFG_STREAM_VFRONT_PORCH GENMASK(31, 16)
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#define HIBMC_DP_VIDEO_PACKET 0x114
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#define HIBMC_DP_CFG_STREAM_TU_SYMBOL_SIZE GENMASK(5, 0)
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#define HIBMC_DP_CFG_STREAM_TU_SYMBOL_FRAC_SIZE GENMASK(9, 6)
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#define HIBMC_DP_CFG_STREAM_SYNC_CALIBRATION GENMASK(31, 20)
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#define HIBMC_DP_VIDEO_MSA0 0x118
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#define HIBMC_DP_CFG_STREAM_VSTART GENMASK(31, 16)
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#define HIBMC_DP_CFG_STREAM_HSTART GENMASK(15, 0)
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#define HIBMC_DP_VIDEO_MSA1 0x11c
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#define HIBMC_DP_VIDEO_MSA2 0x120
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#define HIBMC_DP_VIDEO_HORIZONTAL_SIZE 0X124
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#define HIBMC_DP_CFG_STREAM_HTOTAL_SIZE GENMASK(31, 16)
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#define HIBMC_DP_CFG_STREAM_HBLANK_SIZE GENMASK(15, 0)
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#define HIBMC_DP_COLOR_BAR_CTRL 0x260
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#define HIBMC_DP_COLOR_BAR_CTRL1 0x264
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#define HIBMC_DP_TIMING_GEN_CONFIG0 0x26c
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#define HIBMC_DP_CFG_TIMING_GEN0_HACTIVE GENMASK(31, 16)
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#define HIBMC_DP_CFG_TIMING_GEN0_HBLANK GENMASK(15, 0)
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#define HIBMC_DP_TIMING_GEN_CONFIG2 0x274
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#define HIBMC_DP_CFG_TIMING_GEN0_VACTIVE GENMASK(31, 16)
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#define HIBMC_DP_CFG_TIMING_GEN0_VBLANK GENMASK(15, 0)
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#define HIBMC_DP_TIMING_GEN_CONFIG3 0x278
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#define HIBMC_DP_CFG_TIMING_GEN0_VFRONT_PORCH GENMASK(31, 16)
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#define HIBMC_DP_HDCP_CFG 0x600
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#define HIBMC_DP_DPTX_RST_CTRL 0x700
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#define HIBMC_DP_CFG_AUX_RST_N BIT(4)
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#define HIBMC_DP_DPTX_CLK_CTRL 0x704
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#define HIBMC_DP_DPTX_GCTL0 0x708
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#define HIBMC_DP_CFG_PHY_LANE_NUM GENMASK(2, 1)
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#define HIBMC_DP_INTR_ENABLE 0x720
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#define HIBMC_DP_INTR_ORIGINAL_STATUS 0x728
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#define HIBMC_DP_TIMING_MODEL_CTRL 0x884
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#define HIBMC_DP_CFG_PIXEL_NUM_TIMING_MODE_SEL1 GENMASK(31, 16)
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#define HIBMC_DP_TIMING_SYNC_CTRL 0xFF0
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#define HIBMC_DP_INTSTAT 0x1e0724
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#define HIBMC_DP_INTCLR 0x1e0728
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/* dp serdes reg */
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#define HIBMC_DP_HOST_OFFSET 0x10000
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#define HIBMC_DP_LANE0_RATE_OFFSET 0x4
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#define HIBMC_DP_LANE1_RATE_OFFSET 0xc
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#define HIBMC_DP_LANE_STATUS_OFFSET 0x10
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#define HIBMC_DP_PMA_LANE0_OFFSET 0x18
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#define HIBMC_DP_PMA_LANE1_OFFSET 0x1c
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#define HIBMC_DP_HOST_SERDES_CTRL 0x1f001c
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#define HIBMC_DP_PMA_TXDEEMPH GENMASK(18, 1)
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#define DP_SERDES_DONE 0x3
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/* dp serdes TX-Deempth Configuration */
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#define DP_SERDES_VOL0_PRE0 0x280
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#define DP_SERDES_VOL0_PRE1 0x2300
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#define DP_SERDES_VOL0_PRE2 0x53c0
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#define DP_SERDES_VOL0_PRE3 0x8400
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#define DP_SERDES_VOL1_PRE0 0x380
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#define DP_SERDES_VOL1_PRE1 0x3440
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#define DP_SERDES_VOL1_PRE2 0x6480
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#define DP_SERDES_VOL2_PRE0 0x4c1
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#define DP_SERDES_VOL2_PRE1 0x4500
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#define DP_SERDES_VOL3_PRE0 0x600
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#define DP_SERDES_BW_8_1 0x3
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#define DP_SERDES_BW_5_4 0x2
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#define DP_SERDES_BW_2_7 0x1
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#define DP_SERDES_BW_1_62 0x0
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#endif
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