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3e28a67a85
Pixel normalizer is enabled with normalization factor as 1.0 for
FP16 formats in order to support FBC for those formats in xe3p_lpd.
Previously pixel normalizer gets disabled during the plane disable
routine. But there could be plane format settings without explicitly
calling the plane disable in-between and we could endup keeping the
pixel normalizer enabled for formats which we don't require that.
This is causing crc mismatches in yuv formats and FIFO underruns in
planar formats like NV12. Fix this by updating the pixel normalizer
configuration based on the pixel formats explicitly during the plane
settings arm calls itself - enable it for FP16 and disable it for
other formats in HDR capable planes.
v2: avoid redundant pixel normalization setting updates
v3: moved the normalization factor definition to intel_fbc.c and some
updates to comments
v4: simplified the pixel normalizer setting handling
Fixes: 5298eea7ed ("drm/i915/xe3p_lpd: use pixel normalizer for fp16 formats for FBC")
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patch.msgid.link/20260130095919.107805-1-vinod.govindapillai@intel.com
(cherry picked from commit c0dc68f4e2)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
62 lines
2.0 KiB
C
62 lines
2.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_FBC_H__
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#define __INTEL_FBC_H__
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#include <linux/types.h>
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enum fb_op_origin;
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enum pipe;
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struct intel_atomic_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_display;
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struct intel_dsb;
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struct intel_fbc;
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struct intel_plane;
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struct intel_plane_state;
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enum intel_fbc_id {
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INTEL_FBC_A,
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INTEL_FBC_B,
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INTEL_FBC_C,
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INTEL_FBC_D,
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I915_MAX_FBCS,
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};
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int intel_fbc_atomic_check(struct intel_atomic_state *state);
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int intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state);
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bool intel_fbc_pre_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_fbc_post_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_fbc_init(struct intel_display *display);
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void intel_fbc_cleanup(struct intel_display *display);
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void intel_fbc_sanitize(struct intel_display *display);
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void intel_fbc_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_fbc_disable(struct intel_crtc *crtc);
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void intel_fbc_invalidate(struct intel_display *display,
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unsigned int frontbuffer_bits,
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enum fb_op_origin origin);
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void intel_fbc_flush(struct intel_display *display,
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unsigned int frontbuffer_bits, enum fb_op_origin origin);
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void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane);
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void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display);
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void intel_fbc_read_underrun_dbg_info(struct intel_display *display,
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enum pipe, bool log);
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void intel_fbc_reset_underrun(struct intel_display *display);
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void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc);
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void intel_fbc_debugfs_register(struct intel_display *display);
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void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
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struct intel_plane *plane);
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bool intel_fbc_need_pixel_normalizer(const struct intel_plane_state *plane_state);
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#endif /* __INTEL_FBC_H__ */
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