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9704c1cbed
Add skl_wm0_prefill_lines() (based on the actual state) and skl_wm0_prefill_lines_worst() (worst case estimate) which tell us how many extra lines are needed in prefill for WM0. The returned numbers are in .16 binary fixed point. TODO: skl_wm0_prefill_lines_worst() is a bit rough still v2: Drop all pre-icl FIXMEs since this only gets used for VRR guardband Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20251014191808.12326-8-ville.syrjala@linux.intel.com
87 lines
3.1 KiB
C
87 lines
3.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __SKL_WATERMARK_H__
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#define __SKL_WATERMARK_H__
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#include <linux/types.h>
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enum plane_id;
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struct intel_atomic_state;
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struct intel_crtc;
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struct intel_crtc_state;
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struct intel_dbuf_state;
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struct intel_display;
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struct intel_plane;
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struct intel_plane_state;
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struct skl_ddb_entry;
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struct skl_pipe_wm;
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struct skl_wm_level;
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u8 intel_enabled_dbuf_slices_mask(struct intel_display *display);
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void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
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void intel_sagv_post_plane_update(struct intel_atomic_state *state);
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bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
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bool intel_has_sagv(struct intel_display *display);
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u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,
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const struct skl_ddb_entry *entry);
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bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
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const struct skl_ddb_entry *entries,
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int num_entries, int ignore_idx);
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void intel_wm_state_verify(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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void skl_wm_crtc_disable_noatomic(struct intel_crtc *crtc);
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void skl_wm_plane_disable_noatomic(struct intel_crtc *crtc,
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struct intel_plane *plane);
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void skl_watermark_ipc_init(struct intel_display *display);
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void skl_watermark_ipc_update(struct intel_display *display);
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bool skl_watermark_ipc_enabled(struct intel_display *display);
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void skl_watermark_debugfs_register(struct intel_display *display);
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unsigned int skl_watermark_max_latency(struct intel_display *display,
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int initial_wm_level);
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void skl_wm_init(struct intel_display *display);
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const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
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enum plane_id plane_id,
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int level);
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const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
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enum plane_id plane_id);
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unsigned int skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
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struct intel_plane *plane, int width,
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int height, int cpp);
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struct intel_dbuf_state *
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intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
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int intel_dbuf_num_enabled_slices(const struct intel_dbuf_state *dbuf_state);
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int intel_dbuf_num_active_pipes(const struct intel_dbuf_state *dbuf_state);
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int intel_dbuf_init(struct intel_display *display);
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int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
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int ratio);
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void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
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void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
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void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
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int ratio, bool joined_mbus);
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void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
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void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
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void intel_program_dpkgc_latency(struct intel_atomic_state *state);
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bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state);
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unsigned int skl_wm0_prefill_lines_worst(const struct intel_crtc_state *crtc_state);
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unsigned int skl_wm0_prefill_lines(const struct intel_crtc_state *crtc_state);
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#endif /* __SKL_WATERMARK_H__ */
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