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Most of the soc/intel_gmch.[ch] code is i915 core specific. Split it out to i915_gmch.[ch]. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/f4f8cc931ef2a5958cebe3ca44d40aedad01626f.1763578288.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
142 lines
3.7 KiB
C
142 lines
3.7 KiB
C
// SPDX-License-Identifier: MIT
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/* Copyright © 2025 Intel Corporation */
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#include <linux/pnp.h>
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#include <drm/drm_managed.h>
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#include <drm/drm_print.h>
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#include "i915_drv.h"
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#include "i915_gmch.h"
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#include "intel_pci_config.h"
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static void i915_gmch_bridge_release(struct drm_device *dev, void *bridge)
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{
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pci_dev_put(bridge);
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}
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int i915_gmch_bridge_setup(struct drm_i915_private *i915)
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{
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int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus);
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i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
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if (!i915->gmch.pdev) {
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drm_err(&i915->drm, "bridge device not found\n");
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return -EIO;
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}
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return drmm_add_action_or_reset(&i915->drm, i915_gmch_bridge_release,
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i915->gmch.pdev);
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}
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static int mchbar_reg(struct drm_i915_private *i915)
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{
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return GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
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}
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/* Allocate space for the MCH regs if needed, return nonzero on error */
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static int
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intel_alloc_mchbar_resource(struct drm_i915_private *i915)
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{
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u32 temp_lo, temp_hi = 0;
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u64 mchbar_addr;
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int ret;
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if (GRAPHICS_VER(i915) >= 4)
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pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, &temp_hi);
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pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp_lo);
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mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
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/* If ACPI doesn't have it, assume we need to allocate it ourselves */
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if (IS_ENABLED(CONFIG_PNP) && mchbar_addr &&
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pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
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return 0;
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/* Get some space for it */
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i915->gmch.mch_res.name = "i915 MCHBAR";
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i915->gmch.mch_res.flags = IORESOURCE_MEM;
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ret = pci_bus_alloc_resource(i915->gmch.pdev->bus,
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&i915->gmch.mch_res,
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MCHBAR_SIZE, MCHBAR_SIZE,
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PCIBIOS_MIN_MEM,
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0, pcibios_align_resource,
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i915->gmch.pdev);
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if (ret) {
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drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret);
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i915->gmch.mch_res.start = 0;
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return ret;
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}
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if (GRAPHICS_VER(i915) >= 4)
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pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4,
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upper_32_bits(i915->gmch.mch_res.start));
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pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915),
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lower_32_bits(i915->gmch.mch_res.start));
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return 0;
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}
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/* Setup MCHBAR if possible, return true if we should disable it again */
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void i915_gmch_bar_setup(struct drm_i915_private *i915)
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{
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u32 temp;
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bool enabled;
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if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
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return;
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i915->gmch.mchbar_need_disable = false;
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if (IS_I915G(i915) || IS_I915GM(i915)) {
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pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp);
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enabled = !!(temp & DEVEN_MCHBAR_EN);
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} else {
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pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp);
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enabled = temp & 1;
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}
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/* If it's already enabled, don't have to do anything */
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if (enabled)
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return;
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if (intel_alloc_mchbar_resource(i915))
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return;
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i915->gmch.mchbar_need_disable = true;
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/* Space is allocated or reserved, so enable it. */
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if (IS_I915G(i915) || IS_I915GM(i915)) {
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pci_write_config_dword(i915->gmch.pdev, DEVEN,
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temp | DEVEN_MCHBAR_EN);
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} else {
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pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp);
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pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), temp | 1);
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}
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}
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void i915_gmch_bar_teardown(struct drm_i915_private *i915)
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{
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if (i915->gmch.mchbar_need_disable) {
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if (IS_I915G(i915) || IS_I915GM(i915)) {
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u32 deven_val;
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pci_read_config_dword(i915->gmch.pdev, DEVEN,
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&deven_val);
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deven_val &= ~DEVEN_MCHBAR_EN;
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pci_write_config_dword(i915->gmch.pdev, DEVEN,
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deven_val);
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} else {
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u32 mchbar_val;
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pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915),
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&mchbar_val);
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mchbar_val &= ~1;
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pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915),
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mchbar_val);
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}
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}
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if (i915->gmch.mch_res.start)
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release_resource(&i915->gmch.mch_res);
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}
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