mirror of
https://github.com/torvalds/linux.git
synced 2026-04-26 10:32:25 -04:00
bf4afc53b7
This was done entirely with mindless brute force, using
git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'
to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.
Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.
For the same reason the 'flex' versions will be done as a separate
conversion.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
485 lines
12 KiB
C
485 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2023 Loongson Technology Corporation Limited
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*/
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#include <linux/delay.h>
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#include <drm/drm_managed.h>
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#include <drm/drm_print.h>
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#include "lsdc_drv.h"
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/*
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* The structure of the pixel PLL registers is evolved with times,
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* it can be different across different chip also.
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*/
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/* size is u64, note that all loongson's cpu is little endian.
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* This structure is same for ls7a2000, ls7a1000 and ls2k2000.
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*/
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struct lsdc_pixpll_reg {
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/* Byte 0 ~ Byte 3 */
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unsigned div_out : 7; /* 6 : 0 Output clock divider */
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unsigned _reserved_1_ : 14; /* 20 : 7 */
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unsigned loopc : 9; /* 29 : 21 Clock multiplier */
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unsigned _reserved_2_ : 2; /* 31 : 30 */
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/* Byte 4 ~ Byte 7 */
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unsigned div_ref : 7; /* 38 : 32 Input clock divider */
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unsigned locked : 1; /* 39 PLL locked indicator */
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unsigned sel_out : 1; /* 40 output clk selector */
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unsigned _reserved_3_ : 2; /* 42 : 41 */
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unsigned set_param : 1; /* 43 Trigger the update */
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unsigned bypass : 1; /* 44 */
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unsigned powerdown : 1; /* 45 */
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unsigned _reserved_4_ : 18; /* 46 : 63 no use */
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};
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union lsdc_pixpll_reg_bitmap {
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struct lsdc_pixpll_reg bitmap;
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u32 w[2];
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u64 d;
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};
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struct clk_to_pixpll_parms_lookup_t {
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unsigned int clock; /* kHz */
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unsigned short width;
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unsigned short height;
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unsigned short vrefresh;
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/* Stores parameters for programming the Hardware PLLs */
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unsigned short div_out;
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unsigned short loopc;
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unsigned short div_ref;
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};
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static const struct clk_to_pixpll_parms_lookup_t pixpll_parms_table[] = {
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{148500, 1920, 1080, 60, 11, 49, 3}, /* 1920x1080@60Hz */
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{141750, 1920, 1080, 60, 11, 78, 5}, /* 1920x1080@60Hz */
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/* 1920x1080@50Hz */
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{174500, 1920, 1080, 75, 17, 89, 3}, /* 1920x1080@75Hz */
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{181250, 2560, 1080, 75, 8, 58, 4}, /* 2560x1080@75Hz */
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{297000, 2560, 1080, 30, 8, 95, 4}, /* 3840x2160@30Hz */
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{301992, 1920, 1080, 100, 10, 151, 5}, /* 1920x1080@100Hz */
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{146250, 1680, 1050, 60, 16, 117, 5}, /* 1680x1050@60Hz */
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{135000, 1280, 1024, 75, 10, 54, 4}, /* 1280x1024@75Hz */
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{119000, 1680, 1050, 60, 20, 119, 5}, /* 1680x1050@60Hz */
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{108000, 1600, 900, 60, 15, 81, 5}, /* 1600x900@60Hz */
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/* 1280x1024@60Hz */
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/* 1280x960@60Hz */
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/* 1152x864@75Hz */
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{106500, 1440, 900, 60, 19, 81, 4}, /* 1440x900@60Hz */
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{88750, 1440, 900, 60, 16, 71, 5}, /* 1440x900@60Hz */
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{83500, 1280, 800, 60, 17, 71, 5}, /* 1280x800@60Hz */
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{71000, 1280, 800, 60, 20, 71, 5}, /* 1280x800@60Hz */
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{74250, 1280, 720, 60, 22, 49, 3}, /* 1280x720@60Hz */
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/* 1280x720@50Hz */
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{78750, 1024, 768, 75, 16, 63, 5}, /* 1024x768@75Hz */
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{75000, 1024, 768, 70, 29, 87, 4}, /* 1024x768@70Hz */
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{65000, 1024, 768, 60, 20, 39, 3}, /* 1024x768@60Hz */
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{51200, 1024, 600, 60, 25, 64, 5}, /* 1024x600@60Hz */
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{57284, 832, 624, 75, 24, 55, 4}, /* 832x624@75Hz */
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{49500, 800, 600, 75, 40, 99, 5}, /* 800x600@75Hz */
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{50000, 800, 600, 72, 44, 88, 4}, /* 800x600@72Hz */
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{40000, 800, 600, 60, 30, 36, 3}, /* 800x600@60Hz */
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{36000, 800, 600, 56, 50, 72, 4}, /* 800x600@56Hz */
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{31500, 640, 480, 75, 40, 63, 5}, /* 640x480@75Hz */
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/* 640x480@73Hz */
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{30240, 640, 480, 67, 62, 75, 4}, /* 640x480@67Hz */
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{27000, 720, 576, 50, 50, 54, 4}, /* 720x576@60Hz */
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{25175, 640, 480, 60, 85, 107, 5}, /* 640x480@60Hz */
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{25200, 640, 480, 60, 50, 63, 5}, /* 640x480@60Hz */
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/* 720x480@60Hz */
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};
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static void lsdc_pixel_pll_free(struct drm_device *ddev, void *data)
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{
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struct lsdc_pixpll *this = (struct lsdc_pixpll *)data;
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iounmap(this->mmio);
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kfree(this->priv);
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drm_dbg(ddev, "pixpll private data freed\n");
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}
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/*
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* ioremap the device dependent PLL registers
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*
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* @this: point to the object where this function is called from
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*/
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static int lsdc_pixel_pll_setup(struct lsdc_pixpll * const this)
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{
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struct lsdc_pixpll_parms *pparms;
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this->mmio = ioremap(this->reg_base, this->reg_size);
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if (!this->mmio)
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return -ENOMEM;
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pparms = kzalloc_obj(*pparms);
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if (!pparms) {
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iounmap(this->mmio);
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return -ENOMEM;
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}
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pparms->ref_clock = LSDC_PLL_REF_CLK_KHZ;
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this->priv = pparms;
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return drmm_add_action_or_reset(this->ddev, lsdc_pixel_pll_free, this);
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}
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/*
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* Find a set of pll parameters from a static local table which avoid
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* computing the pll parameter eachtime a modeset is triggered.
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*
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* @this: point to the object where this function is called from
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* @clock: the desired output pixel clock, the unit is kHz
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* @pout: point to where the parameters to store if found
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*
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* Return 0 if success, return -1 if not found.
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*/
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static int lsdc_pixpll_find(struct lsdc_pixpll * const this,
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unsigned int clock,
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struct lsdc_pixpll_parms *pout)
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{
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unsigned int num = ARRAY_SIZE(pixpll_parms_table);
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const struct clk_to_pixpll_parms_lookup_t *pt;
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unsigned int i;
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for (i = 0; i < num; ++i) {
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pt = &pixpll_parms_table[i];
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if (clock == pt->clock) {
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pout->div_ref = pt->div_ref;
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pout->loopc = pt->loopc;
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pout->div_out = pt->div_out;
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return 0;
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}
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}
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drm_dbg_kms(this->ddev, "pixel clock %u: miss\n", clock);
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return -1;
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}
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/*
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* Find a set of pll parameters which have minimal difference with the
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* desired pixel clock frequency. It does that by computing all of the
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* possible combination. Compute the diff and find the combination with
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* minimal diff.
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*
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* clock_out = refclk / div_ref * loopc / div_out
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*
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* refclk is determined by the oscillator mounted on motherboard(100MHz
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* in almost all board)
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*
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* @this: point to the object from where this function is called
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* @clock: the desired output pixel clock, the unit is kHz
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* @pout: point to the out struct of lsdc_pixpll_parms
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*
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* Return 0 if a set of parameter is found, otherwise return the error
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* between clock_kHz we wanted and the most closest candidate with it.
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*/
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static int lsdc_pixel_pll_compute(struct lsdc_pixpll * const this,
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unsigned int clock,
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struct lsdc_pixpll_parms *pout)
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{
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struct lsdc_pixpll_parms *pparms = this->priv;
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unsigned int refclk = pparms->ref_clock;
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const unsigned int tolerance = 1000;
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unsigned int min = tolerance;
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unsigned int div_out, loopc, div_ref;
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unsigned int computed;
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if (!lsdc_pixpll_find(this, clock, pout))
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return 0;
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for (div_out = 6; div_out < 64; div_out++) {
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for (div_ref = 3; div_ref < 6; div_ref++) {
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for (loopc = 6; loopc < 161; loopc++) {
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unsigned int diff = 0;
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if (loopc < 12 * div_ref)
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continue;
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if (loopc > 32 * div_ref)
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continue;
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computed = refclk / div_ref * loopc / div_out;
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if (clock >= computed)
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diff = clock - computed;
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else
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diff = computed - clock;
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if (diff < min) {
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min = diff;
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pparms->div_ref = div_ref;
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pparms->div_out = div_out;
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pparms->loopc = loopc;
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if (diff == 0) {
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*pout = *pparms;
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return 0;
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}
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}
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}
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}
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}
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/* still acceptable */
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if (min < tolerance) {
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*pout = *pparms;
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return 0;
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}
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drm_dbg(this->ddev, "can't find suitable params for %u khz\n", clock);
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return min;
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}
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/* Pixel pll hardware related ops, per display pipe */
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static void __pixpll_rreg(struct lsdc_pixpll *this,
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union lsdc_pixpll_reg_bitmap *dst)
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{
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#if defined(CONFIG_64BIT)
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dst->d = readq(this->mmio);
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#else
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dst->w[0] = readl(this->mmio);
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dst->w[1] = readl(this->mmio + 4);
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#endif
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}
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static void __pixpll_wreg(struct lsdc_pixpll *this,
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union lsdc_pixpll_reg_bitmap *src)
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{
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#if defined(CONFIG_64BIT)
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writeq(src->d, this->mmio);
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#else
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writel(src->w[0], this->mmio);
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writel(src->w[1], this->mmio + 4);
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#endif
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}
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static void __pixpll_ops_powerup(struct lsdc_pixpll * const this)
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{
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union lsdc_pixpll_reg_bitmap pixpll_reg;
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__pixpll_rreg(this, &pixpll_reg);
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pixpll_reg.bitmap.powerdown = 0;
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__pixpll_wreg(this, &pixpll_reg);
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}
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static void __pixpll_ops_powerdown(struct lsdc_pixpll * const this)
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{
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union lsdc_pixpll_reg_bitmap pixpll_reg;
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__pixpll_rreg(this, &pixpll_reg);
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pixpll_reg.bitmap.powerdown = 1;
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__pixpll_wreg(this, &pixpll_reg);
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}
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static void __pixpll_ops_on(struct lsdc_pixpll * const this)
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{
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union lsdc_pixpll_reg_bitmap pixpll_reg;
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__pixpll_rreg(this, &pixpll_reg);
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pixpll_reg.bitmap.sel_out = 1;
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__pixpll_wreg(this, &pixpll_reg);
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}
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static void __pixpll_ops_off(struct lsdc_pixpll * const this)
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{
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union lsdc_pixpll_reg_bitmap pixpll_reg;
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__pixpll_rreg(this, &pixpll_reg);
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pixpll_reg.bitmap.sel_out = 0;
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__pixpll_wreg(this, &pixpll_reg);
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}
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static void __pixpll_ops_bypass(struct lsdc_pixpll * const this)
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{
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union lsdc_pixpll_reg_bitmap pixpll_reg;
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__pixpll_rreg(this, &pixpll_reg);
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pixpll_reg.bitmap.bypass = 1;
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__pixpll_wreg(this, &pixpll_reg);
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}
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static void __pixpll_ops_unbypass(struct lsdc_pixpll * const this)
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{
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union lsdc_pixpll_reg_bitmap pixpll_reg;
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__pixpll_rreg(this, &pixpll_reg);
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pixpll_reg.bitmap.bypass = 0;
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__pixpll_wreg(this, &pixpll_reg);
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}
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static void __pixpll_ops_untoggle_param(struct lsdc_pixpll * const this)
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{
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union lsdc_pixpll_reg_bitmap pixpll_reg;
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__pixpll_rreg(this, &pixpll_reg);
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pixpll_reg.bitmap.set_param = 0;
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__pixpll_wreg(this, &pixpll_reg);
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}
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static void __pixpll_ops_set_param(struct lsdc_pixpll * const this,
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struct lsdc_pixpll_parms const *p)
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{
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union lsdc_pixpll_reg_bitmap pixpll_reg;
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__pixpll_rreg(this, &pixpll_reg);
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pixpll_reg.bitmap.div_ref = p->div_ref;
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pixpll_reg.bitmap.loopc = p->loopc;
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pixpll_reg.bitmap.div_out = p->div_out;
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__pixpll_wreg(this, &pixpll_reg);
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}
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static void __pixpll_ops_toggle_param(struct lsdc_pixpll * const this)
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{
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union lsdc_pixpll_reg_bitmap pixpll_reg;
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__pixpll_rreg(this, &pixpll_reg);
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pixpll_reg.bitmap.set_param = 1;
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__pixpll_wreg(this, &pixpll_reg);
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}
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static void __pixpll_ops_wait_locked(struct lsdc_pixpll * const this)
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{
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union lsdc_pixpll_reg_bitmap pixpll_reg;
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unsigned int counter = 0;
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do {
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__pixpll_rreg(this, &pixpll_reg);
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if (pixpll_reg.bitmap.locked)
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break;
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++counter;
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} while (counter < 2000);
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drm_dbg(this->ddev, "%u loop waited\n", counter);
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}
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/*
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* Update the PLL parameters to the PLL hardware
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*
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* @this: point to the object from which this function is called
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* @pin: point to the struct of lsdc_pixpll_parms passed in
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*
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* return 0 if successful.
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*/
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static int lsdc_pixpll_update(struct lsdc_pixpll * const this,
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struct lsdc_pixpll_parms const *pin)
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{
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__pixpll_ops_bypass(this);
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__pixpll_ops_off(this);
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__pixpll_ops_powerdown(this);
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__pixpll_ops_toggle_param(this);
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__pixpll_ops_set_param(this, pin);
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__pixpll_ops_untoggle_param(this);
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__pixpll_ops_powerup(this);
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udelay(2);
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__pixpll_ops_wait_locked(this);
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__pixpll_ops_on(this);
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__pixpll_ops_unbypass(this);
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return 0;
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}
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static unsigned int lsdc_pixpll_get_freq(struct lsdc_pixpll * const this)
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{
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struct lsdc_pixpll_parms *ppar = this->priv;
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union lsdc_pixpll_reg_bitmap pix_pll_reg;
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unsigned int freq;
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__pixpll_rreg(this, &pix_pll_reg);
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ppar->div_ref = pix_pll_reg.bitmap.div_ref;
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ppar->loopc = pix_pll_reg.bitmap.loopc;
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ppar->div_out = pix_pll_reg.bitmap.div_out;
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freq = ppar->ref_clock / ppar->div_ref * ppar->loopc / ppar->div_out;
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return freq;
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}
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static void lsdc_pixpll_print(struct lsdc_pixpll * const this,
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struct drm_printer *p)
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{
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struct lsdc_pixpll_parms *parms = this->priv;
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drm_printf(p, "div_ref: %u, loopc: %u, div_out: %u\n",
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parms->div_ref, parms->loopc, parms->div_out);
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}
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/*
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* LS7A1000, LS7A2000 and ls2k2000's pixel pll setting register is same,
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* we take this as default, create a new instance if a different model is
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* introduced.
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*/
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static const struct lsdc_pixpll_funcs __pixpll_default_funcs = {
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.setup = lsdc_pixel_pll_setup,
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.compute = lsdc_pixel_pll_compute,
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.update = lsdc_pixpll_update,
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.get_rate = lsdc_pixpll_get_freq,
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.print = lsdc_pixpll_print,
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};
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/* pixel pll initialization */
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int lsdc_pixpll_init(struct lsdc_pixpll * const this,
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struct drm_device *ddev,
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unsigned int index)
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{
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struct lsdc_device *ldev = to_lsdc(ddev);
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const struct lsdc_desc *descp = ldev->descp;
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const struct loongson_gfx_desc *gfx = to_loongson_gfx(descp);
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this->ddev = ddev;
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this->reg_size = 8;
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this->reg_base = gfx->conf_reg_base + gfx->pixpll[index].reg_offset;
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this->funcs = &__pixpll_default_funcs;
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return this->funcs->setup(this);
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}
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