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Ensure that the DMA address of the framebuffer flush page is not larger than its hardware register. On GPUs older than Hopper, the register for the address can hold up to a 40-bit address (right-shifted by 8 so that it fits in the 32-bit register), and on Hopper and later it can be 52 bits (64-bit register where bits 52-63 must be zero). Recently it was discovered that under certain conditions, the flush page could be allocated outside this range. Although this bug was fixed, we can ensure that any future changes to this code don't accidentally generate an invalid page address. Signed-off-by: Timur Tabi <ttabi@nvidia.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251113230323.1271726-2-ttabi@nvidia.com
38 lines
1.2 KiB
C
38 lines
1.2 KiB
C
/* SPDX-License-Identifier: MIT
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*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*/
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#include "priv.h"
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#include <nvhw/drf.h>
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#include <nvhw/ref/gb100/dev_hshub_base.h>
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static void
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gb100_fb_sysmem_flush_page_init(struct nvkm_fb *fb)
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{
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const u32 addr_hi = upper_32_bits(fb->sysmem.flush_page_addr);
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const u32 addr_lo = lower_32_bits(fb->sysmem.flush_page_addr);
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const u32 hshub = DRF_LO(NV_PFB_HSHUB0);
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struct nvkm_device *device = fb->subdev.device;
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// Ensure that the address is within hardware limits
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WARN_ON(fb->sysmem.flush_page_addr > DMA_BIT_MASK(52));
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nvkm_wr32(device, hshub + NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI, addr_hi);
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nvkm_wr32(device, hshub + NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO, addr_lo);
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nvkm_wr32(device, hshub + NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI, addr_hi);
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nvkm_wr32(device, hshub + NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO, addr_lo);
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}
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static const struct nvkm_fb_func
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gb100_fb = {
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.sysmem.flush_page_init = gb100_fb_sysmem_flush_page_init,
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.vidmem.size = ga102_fb_vidmem_size,
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};
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int
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gb100_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
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{
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return r535_fb_new(&gb100_fb, device, type, inst, pfb);
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}
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