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e8372edec9
Add XeLP workaround 16010904313. The description calls for it to be emitted as the indirect context buffer workaround for render and compute, and from the workaround batch buffer for the other engines. Therefore we plug into the previously added respective top level emission functions. The actual command streamer programming sequence differs from what is described in the PRM, in that it assumes the listed LRCA offset was supposed to actually refer to the location of the CTX_TIMESTAMP register instead of LRCA + 0x180c (which is in GPR space). Latter appears to make more sense under the assumption that multiple writes are helping with restoring the CTX_TIMESTAMP register content from the saved context state. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20250711160153.49833-8-tvrtko.ursulin@igalia.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
85 lines
2.9 KiB
C
85 lines
2.9 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_MI_COMMANDS_H_
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#define _XE_MI_COMMANDS_H_
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#include "instructions/xe_instr_defs.h"
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/*
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* MI (Memory Interface) commands are supported by all GT engines. They
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* provide general memory operations and command streamer control. MI commands
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* have a command type of 0x0 (MI_COMMAND) in bits 31:29 of the instruction
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* header dword and a specific MI opcode in bits 28:23.
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*/
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#define MI_OPCODE REG_GENMASK(28, 23)
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#define MI_SUBOPCODE REG_GENMASK(22, 17) /* used with MI_EXPANSION */
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#define __MI_INSTR(opcode) \
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(XE_INSTR_MI | REG_FIELD_PREP(MI_OPCODE, opcode))
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#define MI_NOOP __MI_INSTR(0x0)
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#define MI_USER_INTERRUPT __MI_INSTR(0x2)
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#define MI_ARB_CHECK __MI_INSTR(0x5)
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#define MI_ARB_ON_OFF __MI_INSTR(0x8)
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#define MI_ARB_ENABLE REG_BIT(0)
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#define MI_ARB_DISABLE 0x0
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#define MI_BATCH_BUFFER_END __MI_INSTR(0xA)
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#define MI_TOPOLOGY_FILTER __MI_INSTR(0xD)
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#define MI_FORCE_WAKEUP __MI_INSTR(0x1D)
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#define MI_MATH(n) (__MI_INSTR(0x1A) | XE_INSTR_NUM_DW((n) + 1))
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#define MI_STORE_DATA_IMM __MI_INSTR(0x20)
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#define MI_SDI_GGTT REG_BIT(22)
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#define MI_SDI_LEN_DW GENMASK(9, 0)
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#define MI_SDI_NUM_DW(x) REG_FIELD_PREP(MI_SDI_LEN_DW, (x) + 3 - 2)
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#define MI_SDI_NUM_QW(x) (REG_FIELD_PREP(MI_SDI_LEN_DW, 2 * (x) + 3 - 2) | \
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REG_BIT(21))
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#define MI_LOAD_REGISTER_IMM __MI_INSTR(0x22)
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#define MI_LRI_LRM_CS_MMIO REG_BIT(19)
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#define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
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#define MI_LRI_NUM_REGS(x) XE_INSTR_NUM_DW(2 * (x) + 1)
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#define MI_LRI_FORCE_POSTED REG_BIT(12)
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#define MI_LRI_LEN(x) (((x) & 0xff) + 1)
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#define MI_STORE_REGISTER_MEM (__MI_INSTR(0x24) | XE_INSTR_NUM_DW(4))
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#define MI_SRM_USE_GGTT REG_BIT(22)
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#define MI_SRM_ADD_CS_OFFSET REG_BIT(19)
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#define MI_FLUSH_DW __MI_INSTR(0x26)
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#define MI_FLUSH_DW_PROTECTED_MEM_EN REG_BIT(22)
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#define MI_FLUSH_DW_STORE_INDEX REG_BIT(21)
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#define MI_INVALIDATE_TLB REG_BIT(18)
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#define MI_FLUSH_DW_CCS REG_BIT(16)
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#define MI_FLUSH_DW_OP_STOREDW REG_BIT(14)
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#define MI_FLUSH_DW_LEN_DW REG_GENMASK(5, 0)
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#define MI_FLUSH_IMM_DW REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 4 - 2)
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#define MI_FLUSH_IMM_QW REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 5 - 2)
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#define MI_FLUSH_DW_USE_GTT REG_BIT(2)
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#define MI_LOAD_REGISTER_MEM (__MI_INSTR(0x29) | XE_INSTR_NUM_DW(4))
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#define MI_LRM_USE_GGTT REG_BIT(22)
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#define MI_LRM_ASYNC REG_BIT(21)
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#define MI_LOAD_REGISTER_REG (__MI_INSTR(0x2a) | XE_INSTR_NUM_DW(3))
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#define MI_LRR_DST_CS_MMIO REG_BIT(19)
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#define MI_LRR_SRC_CS_MMIO REG_BIT(18)
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#define MI_COPY_MEM_MEM (__MI_INSTR(0x2e) | XE_INSTR_NUM_DW(5))
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#define MI_COPY_MEM_MEM_SRC_GGTT REG_BIT(22)
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#define MI_COPY_MEM_MEM_DST_GGTT REG_BIT(21)
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#define MI_BATCH_BUFFER_START __MI_INSTR(0x31)
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#define MI_SET_APPID __MI_INSTR(0x0e)
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#define MI_SET_APPID_SESSION_ID_MASK REG_GENMASK(6, 0)
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#define MI_SET_APPID_SESSION_ID(x) REG_FIELD_PREP(MI_SET_APPID_SESSION_ID_MASK, x)
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#endif
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