mirror of
https://github.com/torvalds/linux.git
synced 2026-04-24 09:35:52 -04:00
98466abe4e
Previously, compressible surfaces were required to be non-coherent (allocated as WC) because compression and coherency were mutually exclusive. Starting with Xe3, hardware supports combining compression with 1-way coherency, allowing compressible surfaces to be allocated as WB memory. This provides applications with more efficient memory allocation by avoiding WC allocation overhead that can cause system stuttering and memory management challenges. The implementation adds support for compressed+coherent PAT entry for the xe3_lpg devices and updates the driver logic to handle the new compression capabilities. v2: (Matthew Auld) - Improved error handling with XE_IOCTL_DBG() - Enhanced documentation and comments - Fixed xe_bo_needs_ccs_pages() outdated compression assumptions v3: - Improve WB compression support detection by checking PAT table instead of version check v4: - Add XE_CACHE_WB_COMPRESSION, which simplifies the logic. v5: - Use U16_MAX for the invalid PAT index. (Matthew Auld) Bspec: 71582, 59361, 59399 Cc: Matthew Auld <matthew.auld@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Xin Wang <x.wang@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patch.msgid.link/20260109093007.546784-1-x.wang@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
85 lines
2.0 KiB
C
85 lines
2.0 KiB
C
/* SPDX-License-Identifier: MIT */
|
|
/*
|
|
* Copyright © 2023 Intel Corporation
|
|
*/
|
|
|
|
#ifndef _XE_PAT_H_
|
|
#define _XE_PAT_H_
|
|
|
|
#include <linux/types.h>
|
|
|
|
struct drm_printer;
|
|
struct xe_device;
|
|
struct xe_gt;
|
|
|
|
#define XE_PAT_INVALID_IDX U16_MAX
|
|
|
|
/**
|
|
* struct xe_pat_table_entry - The pat_index encoding and other meta information.
|
|
*/
|
|
struct xe_pat_table_entry {
|
|
/**
|
|
* @value: The platform specific value encoding the various memory
|
|
* attributes (this maps to some fixed pat_index). So things like
|
|
* caching, coherency, compression etc can be encoded here.
|
|
*/
|
|
u32 value;
|
|
|
|
/**
|
|
* @coh_mode: The GPU coherency mode that @value maps to.
|
|
*/
|
|
#define XE_COH_NONE 1
|
|
#define XE_COH_AT_LEAST_1WAY 2
|
|
u16 coh_mode;
|
|
|
|
/**
|
|
* @valid: Set to 1 if the entry is valid, 0 if it's reserved.
|
|
*/
|
|
u16 valid;
|
|
};
|
|
|
|
/**
|
|
* xe_pat_init_early - SW initialization, setting up data based on device
|
|
* @xe: xe device
|
|
*/
|
|
void xe_pat_init_early(struct xe_device *xe);
|
|
|
|
/**
|
|
* xe_pat_init - Program HW PAT table
|
|
* @gt: GT structure
|
|
*/
|
|
void xe_pat_init(struct xe_gt *gt);
|
|
|
|
int xe_pat_dump(struct xe_gt *gt, struct drm_printer *p);
|
|
int xe_pat_dump_sw_config(struct xe_gt *gt, struct drm_printer *p);
|
|
|
|
/**
|
|
* xe_pat_index_get_coh_mode - Extract the coherency mode for the given
|
|
* pat_index.
|
|
* @xe: xe device
|
|
* @pat_index: The pat_index to query
|
|
*/
|
|
u16 xe_pat_index_get_coh_mode(struct xe_device *xe, u16 pat_index);
|
|
|
|
/**
|
|
* xe_pat_index_get_comp_en - Extract the compression enable flag for
|
|
* the given pat_index.
|
|
* @xe: xe device
|
|
* @pat_index: The pat_index to query
|
|
*
|
|
* Return: true if compression is enabled for this pat_index, false otherwise.
|
|
*/
|
|
bool xe_pat_index_get_comp_en(struct xe_device *xe, u16 pat_index);
|
|
|
|
#define XE_L3_POLICY_WB 0 /* Write-back */
|
|
#define XE_L3_POLICY_XD 1 /* WB - Transient Display */
|
|
#define XE_L3_POLICY_UC 3 /* Uncached */
|
|
/**
|
|
* xe_pat_index_get_l3_policy - Extract the L3 policy for the given pat_index.
|
|
* @xe: xe device
|
|
* @pat_index: The pat_index to query
|
|
*/
|
|
u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index);
|
|
|
|
#endif
|